| stats.txt (11106:878dd30741c4) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000053 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000053 # Number of seconds simulated |
| 4sim_ticks 53332000 # Number of ticks simulated 5final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 53334000 # Number of ticks simulated 5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 257745 # Simulator instruction rate (inst/s) 8host_op_rate 257613 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2475242240 # Simulator tick rate (ticks/s) 10host_mem_usage 673312 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host | 7host_inst_rate 497623 # Simulator instruction rate (inst/s) 8host_op_rate 497044 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4772617450 # Simulator tick rate (ticks/s) 10host_mem_usage 679800 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory | 12sim_insts 5548 # Number of instructions simulated 13sim_ops 5548 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory |
| 24system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s) | 24system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) |
| 32system.mem_ctrl.readReqs 394 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 32system.mem_ctrl.readReqs 394 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.mem_ctrl.totGap 53236000 # Total gap between requests | 78system.mem_ctrl.totGap 53238000 # Total gap between requests |
| 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 112 unchanged lines hidden (view full) --- 199system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation | 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 112 unchanged lines hidden (view full) --- 199system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation |
| 207system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing 208system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM | 207system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing 208system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM |
| 209system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers | 209system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers |
| 210system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst | 210system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst |
| 211system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst 213system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s | 212system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst 213system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s |
| 214system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s | 215system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s |
| 216system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage 219system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads 220system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 222system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads 224system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 225system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads 226system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 216system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage 219system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads 220system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 222system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads 224system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 225system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads 226system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.mem_ctrl.avgGap 135116.75 # Average gap between requests | 227system.mem_ctrl.avgGap 135121.83 # Average gap between requests |
| 228system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined 229system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) 230system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) 231system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) 232system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 228system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined 229system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) 230system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) 231system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) 232system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 234system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ) 235system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ) 236system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW) 238system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states | 234system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) 235system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) 236system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) 237system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) 238system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states |
| 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 241system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states | 241system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states |
| 242system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) 244system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) 245system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) 246system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 248system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) 249system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) 250system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) 251system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) 252system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states 253system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states 256system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.workload.num_syscalls 11 # Number of system calls | 242system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) 244system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) 245system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) 246system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) 248system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) 249system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) 250system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) 251system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) 252system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states 253system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 254system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states 256system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.workload.num_syscalls 11 # Number of system calls |
| 258system.cpu.numCycles 53332 # number of cpu cycles simulated | 258system.cpu.numCycles 53334 # number of cpu cycles simulated |
| 259system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 260system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 261system.cpu.committedInsts 5548 # Number of instructions committed 262system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 263system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 264system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 265system.cpu.num_func_calls 146 # number of times a function call or return occured 266system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 267system.cpu.num_int_insts 4660 # number of integer instructions 268system.cpu.num_fp_insts 0 # number of float instructions 269system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 270system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 271system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 272system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 273system.cpu.num_mem_refs 1404 # number of memory refs 274system.cpu.num_load_insts 726 # Number of load instructions 275system.cpu.num_store_insts 678 # Number of store instructions 276system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 259system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 260system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 261system.cpu.committedInsts 5548 # Number of instructions committed 262system.cpu.committedOps 5548 # Number of ops (including micro ops) committed 263system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses 264system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 265system.cpu.num_func_calls 146 # number of times a function call or return occured 266system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls 267system.cpu.num_int_insts 4660 # number of integer instructions 268system.cpu.num_fp_insts 0 # number of float instructions 269system.cpu.num_int_register_reads 10977 # number of times the integer registers were read 270system.cpu.num_int_register_writes 5062 # number of times the integer registers were written 271system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 272system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 273system.cpu.num_mem_refs 1404 # number of memory refs 274system.cpu.num_load_insts 726 # Number of load instructions 275system.cpu.num_store_insts 678 # Number of store instructions 276system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 277system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles | 277system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles |
| 278system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 279system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 280system.cpu.Branches 1187 # Number of branches fetched 281system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 282system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 283system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 284system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 285system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 309system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 310system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 311system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 312system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 313system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 315system.cpu.op_class::total 5591 # Class of executed instruction 316system.cpu.dcache.tags.replacements 0 # number of replacements | 278system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 279system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 280system.cpu.Branches 1187 # Number of branches fetched 281system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction 282system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction 283system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction 284system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction 285system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 309system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction 310system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction 311system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction 312system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction 313system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 314system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 315system.cpu.op_class::total 5591 # Class of executed instruction 316system.cpu.dcache.tags.replacements 0 # number of replacements |
| 317system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use | 317system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use |
| 318system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 319system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 320system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 321system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 318system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 319system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 320system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. 321system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 322system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor | 322system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor |
| 323system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy 325system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 327system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 328system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 329system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 330system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 339system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 340system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 341system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 342system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 343system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 344system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 345system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 346system.cpu.dcache.overall_misses::total 138 # number of overall misses | 323system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy 325system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 327system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 328system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 329system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses 330system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 339system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses 340system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses 341system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses 342system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses 343system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 344system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 345system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 346system.cpu.dcache.overall_misses::total 138 # number of overall misses |
| 347system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles 348system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles 349system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles 350system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles | 347system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles 348system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles 349system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles 350system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles |
| 351system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles 352system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles 353system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles 354system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles 355system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 356system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 364system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 365system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 366system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 367system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 368system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 369system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 370system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses | 351system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles 352system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles 353system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles 354system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles 355system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) 356system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses 364system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses 365system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses 366system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses 367system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses 368system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses 369system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses 370system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses |
| 371system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency 372system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency 373system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency 374system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency | 371system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency 372system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency 373system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency 374system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency |
| 375system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 376system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency 377system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 378system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency 379system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 380system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 381system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 382system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 387system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 388system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 389system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 390system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 391system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 392system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 393system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 394system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses | 375system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 376system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency 377system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency 378system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency 379system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 380system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 381system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 382system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 387system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 388system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 389system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses 390system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses 391system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 392system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 393system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 394system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses |
| 395system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles 396system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles 397system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles 398system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles | 395system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles 396system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles 397system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles 398system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles |
| 399system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles 400system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles 401system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles 402system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles 403system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 404system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 406system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 407system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 408system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 409system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 410system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses | 399system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles 400system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles 401system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles 402system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles 403system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses 404system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses 406system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses 407system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses 408system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses 409system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses 410system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses |
| 411system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency 412system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency 414system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency | 411system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency 412system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency 414system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency |
| 415system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 416system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 418system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 419system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 420system.cpu.icache.tags.replacements 71 # number of replacements | 415system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 416system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency 418system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency 419system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 420system.cpu.icache.tags.replacements 71 # number of replacements |
| 421system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use | 421system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use |
| 422system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 423system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 424system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 425system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 422system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. 423system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. 424system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. 425system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 426system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor 427system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy 428system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy | 426system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor 427system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy 428system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy |
| 429system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 431system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 432system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 433system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 434system.cpu.icache.tags.data_accesses 11443 # Number of data accesses 435system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 436system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 437system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 438system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 439system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 440system.cpu.icache.overall_hits::total 5333 # number of overall hits 441system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 442system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 443system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 444system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 445system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 446system.cpu.icache.overall_misses::total 259 # number of overall misses | 429system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 431system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 432system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id 433system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses 434system.cpu.icache.tags.data_accesses 11443 # Number of data accesses 435system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits 436system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits 437system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits 438system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits 439system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits 440system.cpu.icache.overall_hits::total 5333 # number of overall hits 441system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses 442system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses 443system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses 444system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses 445system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses 446system.cpu.icache.overall_misses::total 259 # number of overall misses |
| 447system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles 448system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles 449system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles 450system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles 451system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles 452system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles | 447system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles 448system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles 449system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles 450system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles 451system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles 452system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles |
| 453system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 454system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 455system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 456system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 457system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 458system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 459system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 460system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 461system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 462system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 463system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 464system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses | 453system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) 454system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) 455system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses 456system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses 457system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses 458system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses 459system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses 460system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses 461system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses 462system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses 463system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses 464system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses |
| 465system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency 466system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency 467system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency 468system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency 469system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency 470system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency | 465system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency 466system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency 467system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency 468system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency 469system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency 470system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency |
| 471system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.icache.fast_writes 0 # number of fast writes performed 478system.cpu.icache.cache_copies 0 # number of cache copies performed 479system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 480system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 481system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 482system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 483system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 484system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses | 471system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.icache.fast_writes 0 # number of fast writes performed 478system.cpu.icache.cache_copies 0 # number of cache copies performed 479system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses 480system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses 481system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses 482system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses 483system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses 484system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses |
| 485system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles 486system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles 487system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles 488system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles 489system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles 490system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles | 485system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles 486system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles 487system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles 488system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles 489system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles 490system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles |
| 491system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 492system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 493system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 494system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 495system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 496system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses | 491system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses 492system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses 493system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses 494system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses 495system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses 496system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses |
| 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency 498system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency 500system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency 502system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency | 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency 498system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 500system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency 502system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency |
| 503system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 503system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 504system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. 505system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 506system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 507system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 508system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 509system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 504system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 505system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 506system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 507system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 508system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 509system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 510system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 511system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) 512system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) 513system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 514system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 515system.l2bus.snoops 0 # Total snoops (count) 516system.l2bus.snoop_fanout::samples 468 # Request fanout histogram | 510system.l2bus.trans_dist::ReadResp 315 # Transaction distribution 511system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 512system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution 513system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution 514system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution 515system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 516system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 517system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) 518system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) 519system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 520system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 521system.l2bus.snoops 0 # Total snoops (count) 522system.l2bus.snoop_fanout::samples 468 # Request fanout histogram |
| 517system.l2bus.snoop_fanout::mean 1 # Request fanout histogram 518system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram | 523system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram 524system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram |
| 519system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 525system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 520system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 521system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram | 526system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram 527system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram |
| 522system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 523system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 528system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 529system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 524system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram | 530system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 525system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 526system.l2bus.snoop_fanout::total 468 # Request fanout histogram 527system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 528system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 529system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 530system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 531system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 532system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 533system.l2cache.tags.replacements 0 # number of replacements | 531system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 532system.l2bus.snoop_fanout::total 468 # Request fanout histogram 533system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) 534system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 535system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) 536system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 537system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) 538system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 539system.l2cache.tags.replacements 0 # number of replacements |
| 534system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use | 540system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use |
| 535system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 536system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. 537system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. 538system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 541system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 542system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. 543system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. 544system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 539system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor 540system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor | 545system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor 546system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor |
| 541system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy 542system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy 543system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy 544system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id 545system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 546system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 547system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id 548system.l2cache.tags.tag_accesses 4130 # Number of tag accesses --- 13 unchanged lines hidden (view full) --- 562system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 563system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 564system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 565system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 566system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 567system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 568system.l2cache.overall_misses::cpu.data 137 # number of overall misses 569system.l2cache.overall_misses::total 394 # number of overall misses | 547system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy 548system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy 549system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy 550system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id 551system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 552system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 553system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id 554system.l2cache.tags.tag_accesses 4130 # Number of tag accesses --- 13 unchanged lines hidden (view full) --- 568system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 569system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses 570system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 571system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 572system.l2cache.demand_misses::total 394 # number of demand (read+write) misses 573system.l2cache.overall_misses::cpu.inst 257 # number of overall misses 574system.l2cache.overall_misses::cpu.data 137 # number of overall misses 575system.l2cache.overall_misses::total 394 # number of overall misses |
| 570system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles 571system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles 572system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles | 576system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles 577system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles 578system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles |
| 573system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles | 579system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles |
| 574system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles 575system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles 576system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles 577system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles 578system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles 579system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles 580system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles | 580system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles 581system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles 582system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles 583system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles 584system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles 585system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles 586system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles |
| 581system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 582system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 583system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 584system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 585system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 586system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 587system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 588system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 595system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 596system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 597system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 598system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 599system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 600system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 601system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 602system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses | 587system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) 588system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) 589system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) 590system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 591system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) 592system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses 593system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 594system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 601system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses 602system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses 603system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses 604system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses 605system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses 606system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses 607system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses 608system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses |
| 603system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency 604system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency 605system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency | 609system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency 610system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency 611system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency |
| 606system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency | 612system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency |
| 607system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency 608system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency 609system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency 610system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency 611system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency 612system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency 613system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency | 613system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency 614system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency 615system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency 616system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency 617system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency 618system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency 619system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency |
| 614system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 615system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 617system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 618system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 619system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.l2cache.fast_writes 0 # number of fast writes performed 621system.l2cache.cache_copies 0 # number of cache copies performed 622system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 623system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 624system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 625system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 626system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 627system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 628system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 629system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 630system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 631system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 632system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses | 620system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 621system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 623system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 624system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 625system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.l2cache.fast_writes 0 # number of fast writes performed 627system.l2cache.cache_copies 0 # number of cache copies performed 628system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses 629system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses 630system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses 631system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 632system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses 633system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 634system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 635system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 636system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 637system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 638system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses |
| 633system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles 634system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles 635system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles | 639system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles 640system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles 641system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles |
| 636system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles | 642system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles |
| 637system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles 638system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles 639system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles 640system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles 641system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles 642system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles 643system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles | 643system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles 644system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles 645system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles 646system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles 647system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles 648system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles 649system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles |
| 644system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 645system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 646system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 647system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 648system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 649system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 650system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 651system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 652system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 653system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 654system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses | 650system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 651system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 652system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses 653system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses 654system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses 655system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses 656system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses 657system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses 658system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses 659system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses 660system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses |
| 655system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency 656system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency 657system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency | 661system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency 662system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency 663system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency |
| 658system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency | 664system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency |
| 659system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency 660system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency 661system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency 662system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency 663system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency 664system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency 665system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency | 665system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency 666system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 667system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency 669system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency 670system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency |
| 666system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 667system.membus.trans_dist::ReadResp 312 # Transaction distribution 668system.membus.trans_dist::ReadExReq 82 # Transaction distribution 669system.membus.trans_dist::ReadExResp 82 # Transaction distribution 670system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 671system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 672system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 673system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- | 672system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 673system.membus.trans_dist::ReadResp 312 # Transaction distribution 674system.membus.trans_dist::ReadExReq 82 # Transaction distribution 675system.membus.trans_dist::ReadExResp 82 # Transaction distribution 676system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution 677system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) 678system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) 679system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- |