3,5c3,5
< sim_seconds 0.000053 # Number of seconds simulated
< sim_ticks 53334000 # Number of ticks simulated
< final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000054 # Number of seconds simulated
> sim_ticks 53605000 # Number of ticks simulated
> final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 532040 # Simulator instruction rate (inst/s)
< host_op_rate 531414 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5103257870 # Simulator tick rate (ticks/s)
< host_mem_usage 634140 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 205629 # Simulator instruction rate (inst/s)
> host_op_rate 205519 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1984690430 # Simulator tick rate (ticks/s)
> host_mem_usage 637752 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 53238000 # Total gap between requests
---
> system.mem_ctrl.totGap 53508000 # Total gap between requests
190,209c190,208
< system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM
211c210
< system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst
213,214c212,213
< system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s
216c215
< system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s
219,220c218,219
< system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads
224c223
< system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads
226c225
< system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads
228,232c227,231
< system.mem_ctrl.avgGap 135121.83 # Average gap between requests
< system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 135807.11 # Average gap between requests
> system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ)
235,239c234,238
< system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states
242c241
< system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states
244,245c243,244
< system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ)
249,253c248,252
< system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states
256c255
< system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states
258c257
< system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
260,261c259,260
< system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 53334 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 53605 # number of cpu cycles simulated
280c279
< system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles
319c318
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
321c320
< system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use
326,328c325,327
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy
335c334
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
352,359c351,358
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles
376,383c375,382
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency
398,405c397,404
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles
414,422c413,421
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
424c423
< system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use
429,431c428,430
< system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy
433,434c432,433
< system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
438c437
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
451,456c450,455
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles
469,474c468,473
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency
487,492c486,491
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles
499,504c498,503
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency
511c510
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
539c538
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
542c541
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
544c543
< system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use
546,547c545,546
< system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks.
549,554c548,553
< system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
556,557c555,556
< system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id
560c559
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
581,591c580,590
< system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles
614,624c613,623
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency
642,652c641,651
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles
664,675c663,680
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
698c703
< system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks)
< sim_seconds 0.000053 # Number of seconds simulated
< sim_ticks 53334000 # Number of ticks simulated
< final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000054 # Number of seconds simulated
> sim_ticks 53605000 # Number of ticks simulated
> final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 532040 # Simulator instruction rate (inst/s)
< host_op_rate 531414 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5103257870 # Simulator tick rate (ticks/s)
< host_mem_usage 634140 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 205629 # Simulator instruction rate (inst/s)
> host_op_rate 205519 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1984690430 # Simulator tick rate (ticks/s)
> host_mem_usage 637752 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 53238000 # Total gap between requests
---
> system.mem_ctrl.totGap 53508000 # Total gap between requests
190,209c190,208
< system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM
211c210
< system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst
213,214c212,213
< system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s
216c215
< system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s
219,220c218,219
< system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads
224c223
< system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads
226c225
< system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads
228,232c227,231
< system.mem_ctrl.avgGap 135121.83 # Average gap between requests
< system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 135807.11 # Average gap between requests
> system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ)
235,239c234,238
< system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states
242c241
< system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states
244,245c243,244
< system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ)
249,253c248,252
< system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states
256c255
< system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states
258c257
< system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
260,261c259,260
< system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 53334 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 53605 # number of cpu cycles simulated
280c279
< system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles
319c318
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
321c320
< system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use
326,328c325,327
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy
335c334
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
352,359c351,358
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles
376,383c375,382
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency
398,405c397,404
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles
414,422c413,421
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
424c423
< system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use
429,431c428,430
< system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy
433,434c432,433
< system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
438c437
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
451,456c450,455
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles
469,474c468,473
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency
487,492c486,491
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles
499,504c498,503
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency
511c510
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
539c538
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
542c541
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
544c543
< system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use
546,547c545,546
< system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks.
549,554c548,553
< system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
556,557c555,556
< system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id
560c559
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
581,591c580,590
< system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles
614,624c613,623
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency
642,652c641,651
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles
664,675c663,680
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states
698c703
< system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks)