4,5c4,5
< sim_ticks 53332000 # Number of ticks simulated
< final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 53334000 # Number of ticks simulated
> final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 257745 # Simulator instruction rate (inst/s)
< host_op_rate 257613 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2475242240 # Simulator tick rate (ticks/s)
< host_mem_usage 673312 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 497623 # Simulator instruction rate (inst/s)
> host_op_rate 497044 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4772617450 # Simulator tick rate (ticks/s)
> host_mem_usage 679800 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
24,31c24,31
< system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.mem_ctrl.totGap 53236000 # Total gap between requests
---
> system.mem_ctrl.totGap 53238000 # Total gap between requests
207,208c207,208
< system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst
212,213c212,213
< system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s
215c215
< system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s
227c227
< system.mem_ctrl.avgGap 135116.75 # Average gap between requests
---
> system.mem_ctrl.avgGap 135121.83 # Average gap between requests
234,238c234,238
< system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states
241c241
< system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states
258c258
< system.cpu.numCycles 53332 # number of cpu cycles simulated
---
> system.cpu.numCycles 53334 # number of cpu cycles simulated
277c277
< system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles
317c317
< system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use
322c322
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor
347,350c347,350
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles
371,374c371,374
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency
395,398c395,398
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles
411,414c411,414
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
421c421
< system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
426,428c426,428
< system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy
447,452c447,452
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles
465,470c465,470
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
485,490c485,490
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles
497,502c497,502
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
503a504,509
> system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
517,518c523,524
< system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
< system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram
> system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram
520,521c526,527
< system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram
---
> system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram
> system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram
524c530
< system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
534c540
< system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use
539,540c545,546
< system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor
---
> system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor
570,572c576,578
< system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles
574,580c580,586
< system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles
---
> system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles
603,605c609,611
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency
607,613c613,619
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency
---
> system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
633,635c639,641
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles
637,643c643,649
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles
655,657c661,663
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency
659,665c665,671
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency
---
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
< sim_ticks 53332000 # Number of ticks simulated
< final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 53334000 # Number of ticks simulated
> final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 257745 # Simulator instruction rate (inst/s)
< host_op_rate 257613 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2475242240 # Simulator tick rate (ticks/s)
< host_mem_usage 673312 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 497623 # Simulator instruction rate (inst/s)
> host_op_rate 497044 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4772617450 # Simulator tick rate (ticks/s)
> host_mem_usage 679800 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
24,31c24,31
< system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.mem_ctrl.totGap 53236000 # Total gap between requests
---
> system.mem_ctrl.totGap 53238000 # Total gap between requests
207,208c207,208
< system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM
210c210
< system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst
212,213c212,213
< system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s
215c215
< system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s
227c227
< system.mem_ctrl.avgGap 135116.75 # Average gap between requests
---
> system.mem_ctrl.avgGap 135121.83 # Average gap between requests
234,238c234,238
< system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states
241c241
< system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states
258c258
< system.cpu.numCycles 53332 # number of cpu cycles simulated
---
> system.cpu.numCycles 53334 # number of cpu cycles simulated
277c277
< system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles
317c317
< system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use
322c322
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor
347,350c347,350
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles
371,374c371,374
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency
395,398c395,398
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles
411,414c411,414
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
421c421
< system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
426,428c426,428
< system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy
447,452c447,452
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles
465,470c465,470
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
485,490c485,490
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles
497,502c497,502
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
503a504,509
> system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
517,518c523,524
< system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
< system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram
> system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram
520,521c526,527
< system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram
---
> system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram
> system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram
524c530
< system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
534c540
< system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use
539,540c545,546
< system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor
---
> system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor
570,572c576,578
< system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles
574,580c580,586
< system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles
---
> system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles
603,605c609,611
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency
607,613c613,619
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency
---
> system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
633,635c639,641
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles
637,643c643,649
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles
655,657c661,663
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency
659,665c665,671
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency
---
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency