1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000053 # Number of seconds simulated
4sim_ticks 53334000 # Number of ticks simulated
5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 388058 # Simulator instruction rate (inst/s)
8host_op_rate 387570 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3721714769 # Simulator tick rate (ticks/s)
10host_mem_usage 636836 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5548 # Number of instructions simulated
13sim_ops 5548 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory
--- 358 unchanged lines hidden (view full) ---
377system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
378system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency
379system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
380system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
381system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
382system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
383system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
384system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
385system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses
386system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses
387system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses
388system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses
389system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
390system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
391system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
392system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
413system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
414system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
415system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
416system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
417system.cpu.icache.tags.replacements 71 # number of replacements
418system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
419system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks.
420system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks.
421system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks.
422system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
423system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
424system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
466system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
467system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
468system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
469system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
470system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
471system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
472system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
473system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
474system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses
475system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses
476system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses
477system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
478system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses
479system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses
480system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
481system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
--- 8 unchanged lines hidden (view full) ---
490system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses
491system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
493system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
494system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
495system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
496system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
497system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
498system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter.
499system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
500system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
501system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
502system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
503system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
504system.l2bus.trans_dist::ReadResp 315 # Transaction distribution
505system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution
--- 106 unchanged lines hidden (view full) ---
612system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
613system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
614system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
615system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
616system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
617system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
618system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
619system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
620system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses
621system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses
622system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses
623system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses
624system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses
625system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
626system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
627system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
--- 28 unchanged lines hidden (view full) ---
656system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency
657system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
658system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
659system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
660system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
661system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
662system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
663system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
664system.membus.trans_dist::ReadResp 312 # Transaction distribution
665system.membus.trans_dist::ReadExReq 82 # Transaction distribution
666system.membus.trans_dist::ReadExResp 82 # Transaction distribution
667system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution
668system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes)
669system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes)
670system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes)
671system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes)
--- 17 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000053 # Number of seconds simulated
4sim_ticks 53334000 # Number of ticks simulated
5final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 388058 # Simulator instruction rate (inst/s)
8host_op_rate 387570 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3721714769 # Simulator tick rate (ticks/s)
10host_mem_usage 636836 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5548 # Number of instructions simulated
13sim_ops 5548 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory
--- 358 unchanged lines hidden (view full) ---
377system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency
378system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency
379system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
380system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
381system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
382system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
383system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
384system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
385system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses
386system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses
387system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses
388system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses
389system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
390system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
391system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
392system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency
410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency
411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency
412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency
413system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
414system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
415system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
416system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
417system.cpu.icache.tags.replacements 71 # number of replacements
418system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
419system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks.
420system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks.
421system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks.
422system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
423system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor
424system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
466system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency
467system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency
468system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
469system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
470system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
471system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
472system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
473system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
474system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses
475system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses
476system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses
477system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
478system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses
479system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses
480system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles
481system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles
--- 8 unchanged lines hidden (view full) ---
490system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses
491system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency
493system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency
494system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
495system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
496system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency
497system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency
498system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter.
499system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
500system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
501system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
502system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
503system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
504system.l2bus.trans_dist::ReadResp 315 # Transaction distribution
505system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution
--- 106 unchanged lines hidden (view full) ---
612system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency
613system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency
614system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
615system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
616system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
617system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
618system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
619system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
620system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses
621system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses
622system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses
623system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses
624system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses
625system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
626system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
627system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
--- 28 unchanged lines hidden (view full) ---
656system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency
657system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency
658system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
659system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
660system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
661system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
662system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
663system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
664system.membus.trans_dist::ReadResp 312 # Transaction distribution
665system.membus.trans_dist::ReadExReq 82 # Transaction distribution
666system.membus.trans_dist::ReadExResp 82 # Transaction distribution
667system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution
668system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes)
669system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes)
670system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes)
671system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes)
--- 17 unchanged lines hidden ---