| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
| 26mem_ranges=0:536870911 | 26mem_ranges=0:536870911:0:0:0:0 |
| 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags | 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags |
| 103addr_ranges=0:18446744073709551615 | 103addr_ranges=0:18446744073709551615:0:0:0:0 |
| 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=SparcTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags | 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=SparcTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags |
| 154addr_ranges=0:18446744073709551615 | 154addr_ranges=0:18446744073709551615:0:0:0:0 |
| 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 106 unchanged lines hidden (view full) --- 269eventq_index=0 270lookup_latency=0 271max_capacity=8388608 272system=system 273 274[system.l2cache] 275type=Cache 276children=tags | 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 106 unchanged lines hidden (view full) --- 269eventq_index=0 270lookup_latency=0 271max_capacity=8388608 272system=system 273 274[system.l2cache] 275type=Cache 276children=tags |
| 277addr_ranges=0:18446744073709551615 | 277addr_ranges=0:18446744073709551615:0:0:0:0 |
| 278assoc=8 279clk_domain=system.clk_domain 280clusivity=mostly_incl 281default_p_state=UNDEFINED 282demand_mshr_reserve=1 283eventq_index=0 284hit_latency=20 285is_read_only=false --- 28 unchanged lines hidden (view full) --- 314p_state_clk_gate_max=1000000000000 315p_state_clk_gate_min=1000 316power_model=Null 317sequential_access=false 318size=262144 319 320[system.mem_ctrl] 321type=DRAMCtrl | 278assoc=8 279clk_domain=system.clk_domain 280clusivity=mostly_incl 281default_p_state=UNDEFINED 282demand_mshr_reserve=1 283eventq_index=0 284hit_latency=20 285is_read_only=false --- 28 unchanged lines hidden (view full) --- 314p_state_clk_gate_max=1000000000000 315p_state_clk_gate_min=1000 316power_model=Null 317sequential_access=false 318size=262144 319 320[system.mem_ctrl] 321type=DRAMCtrl |
| 322IDD0=0.075000 | 322IDD0=0.055000 |
| 323IDD02=0.000000 | 323IDD02=0.000000 |
| 324IDD2N=0.050000 | 324IDD2N=0.032000 |
| 325IDD2N2=0.000000 326IDD2P0=0.000000 327IDD2P02=0.000000 | 325IDD2N2=0.000000 326IDD2P0=0.000000 327IDD2P02=0.000000 |
| 328IDD2P1=0.000000 | 328IDD2P1=0.032000 |
| 329IDD2P12=0.000000 | 329IDD2P12=0.000000 |
| 330IDD3N=0.057000 | 330IDD3N=0.038000 |
| 331IDD3N2=0.000000 332IDD3P0=0.000000 333IDD3P02=0.000000 | 331IDD3N2=0.000000 332IDD3P0=0.000000 333IDD3P02=0.000000 |
| 334IDD3P1=0.000000 | 334IDD3P1=0.038000 |
| 335IDD3P12=0.000000 | 335IDD3P12=0.000000 |
| 336IDD4R=0.187000 | 336IDD4R=0.157000 |
| 337IDD4R2=0.000000 | 337IDD4R2=0.000000 |
| 338IDD4W=0.165000 | 338IDD4W=0.125000 |
| 339IDD4W2=0.000000 | 339IDD4W2=0.000000 |
| 340IDD5=0.220000 | 340IDD5=0.235000 |
| 341IDD52=0.000000 | 341IDD52=0.000000 |
| 342IDD6=0.000000 | 342IDD6=0.020000 |
| 343IDD62=0.000000 344VDD=1.500000 345VDD2=0.000000 346activation_limit=4 347addr_mapping=RoRaBaCoCh 348bank_groups_per_rank=0 349banks_per_rank=8 350burst_length=8 351channels=1 352clk_domain=system.clk_domain 353conf_table_reported=true 354default_p_state=UNDEFINED 355device_bus_width=8 356device_rowbuffer_size=1024 357device_size=536870912 358devices_per_rank=8 359dll=true 360eventq_index=0 361in_addr_map=true | 343IDD62=0.000000 344VDD=1.500000 345VDD2=0.000000 346activation_limit=4 347addr_mapping=RoRaBaCoCh 348bank_groups_per_rank=0 349banks_per_rank=8 350burst_length=8 351channels=1 352clk_domain=system.clk_domain 353conf_table_reported=true 354default_p_state=UNDEFINED 355device_bus_width=8 356device_rowbuffer_size=1024 357device_size=536870912 358devices_per_rank=8 359dll=true 360eventq_index=0 361in_addr_map=true |
| 362kvm_map=true |
|
| 362max_accesses_per_row=16 363mem_sched_policy=frfcfs 364min_writes_per_switch=16 365null=false 366p_state_clk_gate_bins=20 367p_state_clk_gate_max=1000000000000 368p_state_clk_gate_min=1000 369page_policy=open_adaptive 370power_model=Null | 363max_accesses_per_row=16 364mem_sched_policy=frfcfs 365min_writes_per_switch=16 366null=false 367p_state_clk_gate_bins=20 368p_state_clk_gate_max=1000000000000 369p_state_clk_gate_min=1000 370page_policy=open_adaptive 371power_model=Null |
| 371range=0:536870911 | 372range=0:536870911:0:0:0:0 |
| 372ranks_per_channel=2 373read_buffer_size=32 374static_backend_latency=10000 375static_frontend_latency=10000 376tBURST=5000 377tCCD_L=0 378tCK=1250 379tCL=13750 --- 5 unchanged lines hidden (view full) --- 385tRP=13750 386tRRD=6000 387tRRD_L=0 388tRTP=7500 389tRTW=2500 390tWR=15000 391tWTR=7500 392tXAW=30000 | 373ranks_per_channel=2 374read_buffer_size=32 375static_backend_latency=10000 376static_frontend_latency=10000 377tBURST=5000 378tCCD_L=0 379tCK=1250 380tCL=13750 --- 5 unchanged lines hidden (view full) --- 386tRP=13750 387tRRD=6000 388tRRD_L=0 389tRTP=7500 390tRTW=2500 391tWR=15000 392tWTR=7500 393tXAW=30000 |
| 393tXP=0 | 394tXP=6000 |
| 394tXPDLL=0 | 395tXPDLL=0 |
| 395tXS=0 | 396tXS=270000 |
| 396tXSDLL=0 397write_buffer_size=64 398write_high_thresh_perc=85 399write_low_thresh_perc=50 400port=system.membus.master[0] 401 402[system.membus] 403type=CoherentXBar | 397tXSDLL=0 398write_buffer_size=64 399write_high_thresh_perc=85 400write_low_thresh_perc=50 401port=system.membus.master[0] 402 403[system.membus] 404type=CoherentXBar |
| 405children=snoop_filter |
|
| 404clk_domain=system.clk_domain 405default_p_state=UNDEFINED 406eventq_index=0 407forward_latency=4 408frontend_latency=3 409p_state_clk_gate_bins=20 410p_state_clk_gate_max=1000000000000 411p_state_clk_gate_min=1000 412point_of_coherency=true 413power_model=Null 414response_latency=2 | 406clk_domain=system.clk_domain 407default_p_state=UNDEFINED 408eventq_index=0 409forward_latency=4 410frontend_latency=3 411p_state_clk_gate_bins=20 412p_state_clk_gate_max=1000000000000 413p_state_clk_gate_min=1000 414point_of_coherency=true 415power_model=Null 416response_latency=2 |
| 415snoop_filter=Null | 417snoop_filter=system.membus.snoop_filter |
| 416snoop_response_latency=4 417system=system 418use_default_range=false 419width=16 420master=system.mem_ctrl.port 421slave=system.l2cache.mem_side system.system_port 422 | 418snoop_response_latency=4 419system=system 420use_default_range=false 421width=16 422master=system.mem_ctrl.port 423slave=system.l2cache.mem_side system.system_port 424 |
| 425[system.membus.snoop_filter] 426type=SnoopFilter 427eventq_index=0 428lookup_latency=1 429max_capacity=8388608 430system=system 431 |
|