config.ini (11312:3d7a85d71bd1) config.ini (11440:76b5639162af)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 15 unchanged lines hidden (view full) ---

24mem_mode=timing
25mem_ranges=0:536870911
26memories=system.mem_ctrl
27mmap_using_noreserve=false
28multi_thread=false
29num_work_ids=16
30readfile=
31symbolfile=
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 15 unchanged lines hidden (view full) ---

24mem_mode=timing
25mem_ranges=0:536870911
26memories=system.mem_ctrl
27mmap_using_noreserve=false
28multi_thread=false
29num_work_ids=16
30readfile=
31symbolfile=
32thermal_components=
33thermal_model=Null
32work_begin_ckpt_count=0
33work_begin_cpu_id_exit=-1
34work_begin_exit_count=0
35work_cpus_ckpt_count=0
36work_end_ckpt_count=0
37work_end_exit_count=0
38work_item_id=-1
39system_port=system.membus.slave[1]

--- 49 unchanged lines hidden (view full) ---

89type=Cache
90children=tags
91addr_ranges=0:18446744073709551615
92assoc=2
93clk_domain=system.clk_domain
94clusivity=mostly_incl
95demand_mshr_reserve=1
96eventq_index=0
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
38work_end_ckpt_count=0
39work_end_exit_count=0
40work_item_id=-1
41system_port=system.membus.slave[1]

--- 49 unchanged lines hidden (view full) ---

91type=Cache
92children=tags
93addr_ranges=0:18446744073709551615
94assoc=2
95clk_domain=system.clk_domain
96clusivity=mostly_incl
97demand_mshr_reserve=1
98eventq_index=0
97forward_snoops=true
98hit_latency=2
99is_read_only=false
100max_miss_count=0
101mshrs=4
102prefetch_on_access=false
103prefetcher=Null
104response_latency=2
105sequential_access=false

--- 25 unchanged lines hidden (view full) ---

131type=Cache
132children=tags
133addr_ranges=0:18446744073709551615
134assoc=2
135clk_domain=system.clk_domain
136clusivity=mostly_incl
137demand_mshr_reserve=1
138eventq_index=0
99hit_latency=2
100is_read_only=false
101max_miss_count=0
102mshrs=4
103prefetch_on_access=false
104prefetcher=Null
105response_latency=2
106sequential_access=false

--- 25 unchanged lines hidden (view full) ---

132type=Cache
133children=tags
134addr_ranges=0:18446744073709551615
135assoc=2
136clk_domain=system.clk_domain
137clusivity=mostly_incl
138demand_mshr_reserve=1
139eventq_index=0
139forward_snoops=true
140hit_latency=2
141is_read_only=false
142max_miss_count=0
143mshrs=4
144prefetch_on_access=false
145prefetcher=Null
146response_latency=2
147sequential_access=false

--- 66 unchanged lines hidden (view full) ---

214
215[system.l2bus]
216type=CoherentXBar
217children=snoop_filter
218clk_domain=system.clk_domain
219eventq_index=0
220forward_latency=0
221frontend_latency=1
140hit_latency=2
141is_read_only=false
142max_miss_count=0
143mshrs=4
144prefetch_on_access=false
145prefetcher=Null
146response_latency=2
147sequential_access=false

--- 66 unchanged lines hidden (view full) ---

214
215[system.l2bus]
216type=CoherentXBar
217children=snoop_filter
218clk_domain=system.clk_domain
219eventq_index=0
220forward_latency=0
221frontend_latency=1
222point_of_coherency=false
222response_latency=1
223snoop_filter=system.l2bus.snoop_filter
224snoop_response_latency=1
225system=system
226use_default_range=false
227width=32
228master=system.l2cache.cpu_side
229slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

--- 9 unchanged lines hidden (view full) ---

239type=Cache
240children=tags
241addr_ranges=0:18446744073709551615
242assoc=8
243clk_domain=system.clk_domain
244clusivity=mostly_incl
245demand_mshr_reserve=1
246eventq_index=0
223response_latency=1
224snoop_filter=system.l2bus.snoop_filter
225snoop_response_latency=1
226system=system
227use_default_range=false
228width=32
229master=system.l2cache.cpu_side
230slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

--- 9 unchanged lines hidden (view full) ---

240type=Cache
241children=tags
242addr_ranges=0:18446744073709551615
243assoc=8
244clk_domain=system.clk_domain
245clusivity=mostly_incl
246demand_mshr_reserve=1
247eventq_index=0
247forward_snoops=true
248hit_latency=20
249is_read_only=false
250max_miss_count=0
251mshrs=20
252prefetch_on_access=false
253prefetcher=Null
254response_latency=20
255sequential_access=false

--- 94 unchanged lines hidden (view full) ---

350port=system.membus.master[0]
351
352[system.membus]
353type=CoherentXBar
354clk_domain=system.clk_domain
355eventq_index=0
356forward_latency=4
357frontend_latency=3
248hit_latency=20
249is_read_only=false
250max_miss_count=0
251mshrs=20
252prefetch_on_access=false
253prefetcher=Null
254response_latency=20
255sequential_access=false

--- 94 unchanged lines hidden (view full) ---

350port=system.membus.master[0]
351
352[system.membus]
353type=CoherentXBar
354clk_domain=system.clk_domain
355eventq_index=0
356forward_latency=4
357frontend_latency=3
358point_of_coherency=true
358response_latency=2
359snoop_filter=Null
360snoop_response_latency=4
361system=system
362use_default_range=false
363width=16
364master=system.mem_ctrl.port
365slave=system.l2cache.mem_side system.system_port
366
359response_latency=2
360snoop_filter=Null
361snoop_response_latency=4
362system=system
363use_default_range=false
364width=16
365master=system.mem_ctrl.port
366slave=system.l2cache.mem_side system.system_port
367