1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 77 unchanged lines hidden (view full) ---

86p_state_clk_gate_max=1000000000000
87p_state_clk_gate_min=1000
88power_model=Null
89profile=0
90progress_interval=0
91simpoint_start_insts=
92socket_id=0
93switched_out=false
94system=system
95tracer=system.cpu.tracer
96workload=system.cpu.workload
97dcache_port=system.cpu.dcache.cpu_side
98icache_port=system.cpu.icache.cpu_side
99
100[system.cpu.dcache]
101type=Cache
102children=tags
103addr_ranges=0:18446744073709551615:0:0:0:0
104assoc=2
105clk_domain=system.clk_domain
106clusivity=mostly_incl
107default_p_state=UNDEFINED
108demand_mshr_reserve=1
109eventq_index=0
110hit_latency=2
111is_read_only=false
112max_miss_count=0
113mshrs=4
114p_state_clk_gate_bins=20
115p_state_clk_gate_max=1000000000000
116p_state_clk_gate_min=1000
117power_model=Null
118prefetch_on_access=false
119prefetcher=Null
120response_latency=2
121sequential_access=false
122size=65536
123system=system
124tags=system.cpu.dcache.tags
125tgts_per_mshr=20
126write_buffers=8
127writeback_clean=false
128cpu_side=system.cpu.dcache_port
129mem_side=system.l2bus.slave[1]
130
131[system.cpu.dcache.tags]
132type=LRU
133assoc=2
134block_size=64
135clk_domain=system.clk_domain
136default_p_state=UNDEFINED
137eventq_index=0
138hit_latency=2
139p_state_clk_gate_bins=20
140p_state_clk_gate_max=1000000000000
141p_state_clk_gate_min=1000
142power_model=Null
143sequential_access=false
144size=65536
145
146[system.cpu.dtb]
147type=SparcTLB
148eventq_index=0
149size=64
150
151[system.cpu.icache]
152type=Cache
153children=tags
154addr_ranges=0:18446744073709551615:0:0:0:0
155assoc=2
156clk_domain=system.clk_domain
157clusivity=mostly_incl
158default_p_state=UNDEFINED
159demand_mshr_reserve=1
160eventq_index=0
161hit_latency=2
162is_read_only=false
163max_miss_count=0
164mshrs=4
165p_state_clk_gate_bins=20
166p_state_clk_gate_max=1000000000000
167p_state_clk_gate_min=1000
168power_model=Null
169prefetch_on_access=false
170prefetcher=Null
171response_latency=2
172sequential_access=false
173size=16384
174system=system
175tags=system.cpu.icache.tags
176tgts_per_mshr=20
177write_buffers=8
178writeback_clean=false
179cpu_side=system.cpu.icache_port
180mem_side=system.l2bus.slave[0]
181
182[system.cpu.icache.tags]
183type=LRU
184assoc=2
185block_size=64
186clk_domain=system.clk_domain
187default_p_state=UNDEFINED
188eventq_index=0
189hit_latency=2
190p_state_clk_gate_bins=20
191p_state_clk_gate_max=1000000000000
192p_state_clk_gate_min=1000
193power_model=Null
194sequential_access=false
195size=16384
196
197[system.cpu.interrupts]
198type=SparcInterrupts
199eventq_index=0
200
201[system.cpu.isa]
202type=SparcISA
203eventq_index=0
204
205[system.cpu.itb]
206type=SparcTLB
207eventq_index=0
208size=64
209
210[system.cpu.tracer]
211type=ExeTracer
212eventq_index=0
213
214[system.cpu.workload]
215type=LiveProcess
216cmd=tests/test-progs/hello/bin/sparc/linux/hello
217cwd=
218drivers=
219egid=100
220env=
221errout=cerr
222euid=100
223eventq_index=0
224executable=
225gid=100
226input=cin
227kvmInSE=false
228max_stack_size=67108864
229output=cout
230pid=100
231ppid=99
232simpoint=0
233system=system
234uid=100
235useArchPT=false
236
237[system.dvfs_handler]
238type=DVFSHandler
239domains=

--- 33 unchanged lines hidden (view full) ---

273
274[system.l2cache]
275type=Cache
276children=tags
277addr_ranges=0:18446744073709551615:0:0:0:0
278assoc=8
279clk_domain=system.clk_domain
280clusivity=mostly_incl
281default_p_state=UNDEFINED
282demand_mshr_reserve=1
283eventq_index=0
284hit_latency=20
285is_read_only=false
286max_miss_count=0
287mshrs=20
288p_state_clk_gate_bins=20
289p_state_clk_gate_max=1000000000000
290p_state_clk_gate_min=1000
291power_model=Null
292prefetch_on_access=false
293prefetcher=Null
294response_latency=20
295sequential_access=false
296size=262144
297system=system
298tags=system.l2cache.tags
299tgts_per_mshr=12
300write_buffers=8
301writeback_clean=false
302cpu_side=system.l2bus.master[0]
303mem_side=system.membus.slave[0]
304
305[system.l2cache.tags]
306type=LRU
307assoc=8
308block_size=64
309clk_domain=system.clk_domain
310default_p_state=UNDEFINED
311eventq_index=0
312hit_latency=20
313p_state_clk_gate_bins=20
314p_state_clk_gate_max=1000000000000
315p_state_clk_gate_min=1000
316power_model=Null
317sequential_access=false
318size=262144
319
320[system.mem_ctrl]
321type=DRAMCtrl
322IDD0=0.055000
323IDD02=0.000000
324IDD2N=0.032000
325IDD2N2=0.000000
326IDD2P0=0.000000

--- 105 unchanged lines hidden ---