1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
26mem_ranges=0:536870911:0:0:0:0 |
27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 112 unchanged lines hidden (view full) --- 147domains= 148enable=false 149eventq_index=0 150sys_clk_domain=system.clk_domain 151transition_latency=100000000 152 153[system.mem_ctrl] 154type=DRAMCtrl |
155IDD0=0.055000 |
156IDD02=0.000000 |
157IDD2N=0.032000 |
158IDD2N2=0.000000 159IDD2P0=0.000000 160IDD2P02=0.000000 |
161IDD2P1=0.032000 |
162IDD2P12=0.000000 |
163IDD3N=0.038000 |
164IDD3N2=0.000000 165IDD3P0=0.000000 166IDD3P02=0.000000 |
167IDD3P1=0.038000 |
168IDD3P12=0.000000 |
169IDD4R=0.157000 |
170IDD4R2=0.000000 |
171IDD4W=0.125000 |
172IDD4W2=0.000000 |
173IDD5=0.235000 |
174IDD52=0.000000 |
175IDD6=0.020000 |
176IDD62=0.000000 177VDD=1.500000 178VDD2=0.000000 179activation_limit=4 180addr_mapping=RoRaBaCoCh 181bank_groups_per_rank=0 182banks_per_rank=8 183burst_length=8 184channels=1 185clk_domain=system.clk_domain 186conf_table_reported=true 187default_p_state=UNDEFINED 188device_bus_width=8 189device_rowbuffer_size=1024 190device_size=536870912 191devices_per_rank=8 192dll=true 193eventq_index=0 194in_addr_map=true |
195kvm_map=true |
196max_accesses_per_row=16 197mem_sched_policy=frfcfs 198min_writes_per_switch=16 199null=false 200p_state_clk_gate_bins=20 201p_state_clk_gate_max=1000000000000 202p_state_clk_gate_min=1000 203page_policy=open_adaptive 204power_model=Null |
205range=0:536870911:0:0:0:0 |
206ranks_per_channel=2 207read_buffer_size=32 208static_backend_latency=10000 209static_frontend_latency=10000 210tBURST=5000 211tCCD_L=0 212tCK=1250 213tCL=13750 --- 5 unchanged lines hidden (view full) --- 219tRP=13750 220tRRD=6000 221tRRD_L=0 222tRTP=7500 223tRTW=2500 224tWR=15000 225tWTR=7500 226tXAW=30000 |
227tXP=6000 |
228tXPDLL=0 |
229tXS=270000 |
230tXSDLL=0 231write_buffer_size=64 232write_high_thresh_perc=85 233write_low_thresh_perc=50 234port=system.membus.master[0] 235 236[system.membus] 237type=CoherentXBar |
238children=snoop_filter |
239clk_domain=system.clk_domain 240default_p_state=UNDEFINED 241eventq_index=0 242forward_latency=4 243frontend_latency=3 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247point_of_coherency=true 248power_model=Null 249response_latency=2 |
250snoop_filter=system.membus.snoop_filter |
251snoop_response_latency=4 252system=system 253use_default_range=false 254width=16 255master=system.mem_ctrl.port 256slave=system.cpu.icache_port system.cpu.dcache_port system.system_port 257 |
258[system.membus.snoop_filter] 259type=SnoopFilter 260eventq_index=0 261lookup_latency=1 262max_capacity=8388608 263system=system 264 |