1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=0:536870911
27memories=system.mem_ctrl
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null

--- 112 unchanged lines hidden (view full) ---

147domains=
148enable=false
149eventq_index=0
150sys_clk_domain=system.clk_domain
151transition_latency=100000000
152
153[system.mem_ctrl]
154type=DRAMCtrl
155IDD0=0.075000
156IDD02=0.000000
157IDD2N=0.050000
158IDD2N2=0.000000
159IDD2P0=0.000000
160IDD2P02=0.000000
161IDD2P1=0.000000
162IDD2P12=0.000000
163IDD3N=0.057000
164IDD3N2=0.000000
165IDD3P0=0.000000
166IDD3P02=0.000000
167IDD3P1=0.000000
168IDD3P12=0.000000
169IDD4R=0.187000
170IDD4R2=0.000000
171IDD4W=0.165000
172IDD4W2=0.000000
173IDD5=0.220000
174IDD52=0.000000
175IDD6=0.000000
176IDD62=0.000000
177VDD=1.500000
178VDD2=0.000000
179activation_limit=4
180addr_mapping=RoRaBaCoCh
181bank_groups_per_rank=0
182banks_per_rank=8
183burst_length=8
184channels=1
185clk_domain=system.clk_domain
186conf_table_reported=true
187default_p_state=UNDEFINED
188device_bus_width=8
189device_rowbuffer_size=1024
190device_size=536870912
191devices_per_rank=8
192dll=true
193eventq_index=0
194in_addr_map=true
195max_accesses_per_row=16
196mem_sched_policy=frfcfs
197min_writes_per_switch=16
198null=false
199p_state_clk_gate_bins=20
200p_state_clk_gate_max=1000000000000
201p_state_clk_gate_min=1000
202page_policy=open_adaptive
203power_model=Null
204range=0:536870911
205ranks_per_channel=2
206read_buffer_size=32
207static_backend_latency=10000
208static_frontend_latency=10000
209tBURST=5000
210tCCD_L=0
211tCK=1250
212tCL=13750

--- 5 unchanged lines hidden (view full) ---

218tRP=13750
219tRRD=6000
220tRRD_L=0
221tRTP=7500
222tRTW=2500
223tWR=15000
224tWTR=7500
225tXAW=30000
226tXP=0
227tXPDLL=0
228tXS=0
229tXSDLL=0
230write_buffer_size=64
231write_high_thresh_perc=85
232write_low_thresh_perc=50
233port=system.membus.master[0]
234
235[system.membus]
236type=CoherentXBar
237clk_domain=system.clk_domain
238default_p_state=UNDEFINED
239eventq_index=0
240forward_latency=4
241frontend_latency=3
242p_state_clk_gate_bins=20
243p_state_clk_gate_max=1000000000000
244p_state_clk_gate_min=1000
245point_of_coherency=true
246power_model=Null
247response_latency=2
248snoop_filter=Null
249snoop_response_latency=4
250system=system
251use_default_range=false
252width=16
253master=system.mem_ctrl.port
254slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
255