| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000059 # Number of seconds simulated 4sim_ticks 58892000 # Number of ticks simulated 5final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000059 # Number of seconds simulated 4sim_ticks 58892000 # Number of ticks simulated 5final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 509573 # Simulator instruction rate (inst/s) 8host_op_rate 509069 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5309891860 # Simulator tick rate (ticks/s) 10host_mem_usage 632772 # Number of bytes of host memory used | 7host_inst_rate 486513 # Simulator instruction rate (inst/s) 8host_op_rate 486102 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5071440381 # Simulator tick rate (ticks/s) 10host_mem_usage 676956 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.dtb.read_hits 0 # DTB read hits 253system.cpu.dtb.read_misses 0 # DTB read misses 254system.cpu.dtb.read_accesses 0 # DTB read accesses 255system.cpu.dtb.write_hits 0 # DTB write hits 256system.cpu.dtb.write_misses 0 # DTB write misses 257system.cpu.dtb.write_accesses 0 # DTB write accesses 258system.cpu.dtb.hits 0 # DTB hits 259system.cpu.dtb.misses 0 # DTB misses 260system.cpu.dtb.accesses 0 # DTB accesses 261system.cpu.itb.read_hits 0 # DTB read hits 262system.cpu.itb.read_misses 0 # DTB read misses 263system.cpu.itb.read_accesses 0 # DTB read accesses 264system.cpu.itb.write_hits 0 # DTB write hits 265system.cpu.itb.write_misses 0 # DTB write misses 266system.cpu.itb.write_accesses 0 # DTB write accesses 267system.cpu.itb.hits 0 # DTB hits 268system.cpu.itb.misses 0 # DTB misses 269system.cpu.itb.accesses 0 # DTB accesses 270system.cpu.workload.num_syscalls 7 # Number of system calls | 254system.cpu.dtb.read_hits 0 # DTB read hits 255system.cpu.dtb.read_misses 0 # DTB read misses 256system.cpu.dtb.read_accesses 0 # DTB read accesses 257system.cpu.dtb.write_hits 0 # DTB write hits 258system.cpu.dtb.write_misses 0 # DTB write misses 259system.cpu.dtb.write_accesses 0 # DTB write accesses 260system.cpu.dtb.hits 0 # DTB hits 261system.cpu.dtb.misses 0 # DTB misses 262system.cpu.dtb.accesses 0 # DTB accesses 263system.cpu.itb.read_hits 0 # DTB read hits 264system.cpu.itb.read_misses 0 # DTB read misses 265system.cpu.itb.read_accesses 0 # DTB read accesses 266system.cpu.itb.write_hits 0 # DTB write hits 267system.cpu.itb.write_misses 0 # DTB write misses 268system.cpu.itb.write_accesses 0 # DTB write accesses 269system.cpu.itb.hits 0 # DTB hits 270system.cpu.itb.misses 0 # DTB misses 271system.cpu.itb.accesses 0 # DTB accesses 272system.cpu.workload.num_syscalls 7 # Number of system calls |
| 273system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states |
|
| 271system.cpu.numCycles 58892 # number of cpu cycles simulated 272system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 273system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 274system.cpu.committedInsts 5641 # Number of instructions committed 275system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 276system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 277system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 278system.cpu.num_func_calls 191 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 321system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 322system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 323system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 324system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 325system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 326system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 327system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 328system.cpu.op_class::total 5642 # Class of executed instruction | 274system.cpu.numCycles 58892 # number of cpu cycles simulated 275system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 276system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 277system.cpu.committedInsts 5641 # Number of instructions committed 278system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 279system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 280system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 281system.cpu.num_func_calls 191 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 324system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 325system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 326system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 327system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 328system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 329system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 330system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 331system.cpu.op_class::total 5642 # Class of executed instruction |
| 332system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 329system.cpu.dcache.tags.replacements 0 # number of replacements 330system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use 331system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 332system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 333system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 334system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 335system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor 336system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy 337system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy 338system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 339system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 340system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 341system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id 342system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 343system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses | 333system.cpu.dcache.tags.replacements 0 # number of replacements 334system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use 335system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 336system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 337system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 338system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 339system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor 340system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy 341system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy 342system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 343system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 344system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 345system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id 346system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 347system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses |
| 348system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 344system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 345system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 346system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 347system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 348system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 349system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 350system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 351system.cpu.dcache.overall_hits::total 1899 # number of overall hits --- 70 unchanged lines hidden (view full) --- 422system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency 423system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency 424system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency 425system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency 426system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency 427system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency 428system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency 429system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency | 349system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 350system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 351system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 352system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 353system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 354system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 355system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 356system.cpu.dcache.overall_hits::total 1899 # number of overall hits --- 70 unchanged lines hidden (view full) --- 427system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency 428system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency 429system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency 430system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency 431system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency 432system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency 433system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency 434system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency |
| 435system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 430system.cpu.icache.tags.replacements 94 # number of replacements 431system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use 432system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. 433system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. 434system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. 435system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor 437system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy 438system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy 439system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id 440system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 441system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id 442system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id 443system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses 444system.cpu.icache.tags.data_accesses 11583 # Number of data accesses | 436system.cpu.icache.tags.replacements 94 # number of replacements 437system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use 438system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. 439system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. 440system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. 441system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 442system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor 443system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy 444system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy 445system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id 446system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 447system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id 448system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id 449system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses 450system.cpu.icache.tags.data_accesses 11583 # Number of data accesses |
| 451system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 445system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits 446system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits 447system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits 448system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits 449system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits 450system.cpu.icache.overall_hits::total 5346 # number of overall hits 451system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses 452system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 509system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency 510system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency 511system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. 512system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 513system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 514system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 515system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 516system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 452system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits 453system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits 454system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits 455system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits 456system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits 457system.cpu.icache.overall_hits::total 5346 # number of overall hits 458system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses 459system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 516system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency 517system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency 518system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. 519system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 520system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 521system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 522system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 523system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 524system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 517system.l2bus.trans_dist::ReadResp 384 # Transaction distribution 518system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution 519system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution 520system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution 521system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution 522system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 523system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 524system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 538system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram 539system.l2bus.snoop_fanout::total 434 # Request fanout histogram 540system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) 541system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 542system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) 543system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 544system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) 545system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) | 525system.l2bus.trans_dist::ReadResp 384 # Transaction distribution 526system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution 527system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution 528system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution 529system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution 530system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 531system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 532system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 546system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram 547system.l2bus.snoop_fanout::total 434 # Request fanout histogram 548system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) 549system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 550system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) 551system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 552system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) 553system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 554system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
|
| 546system.l2cache.tags.replacements 0 # number of replacements 547system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use 548system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. 549system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 550system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. 551system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 552system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor 553system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor 554system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy 555system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy 556system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy 557system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 558system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 559system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 560system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id 561system.l2cache.tags.tag_accesses 4654 # Number of tag accesses 562system.l2cache.tags.data_accesses 4654 # Number of data accesses | 555system.l2cache.tags.replacements 0 # number of replacements 556system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use 557system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. 558system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 559system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. 560system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 561system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor 562system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor 563system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy 564system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy 565system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy 566system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 567system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 568system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 569system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id 570system.l2cache.tags.tag_accesses 4654 # Number of tag accesses 571system.l2cache.tags.data_accesses 4654 # Number of data accesses |
| 572system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
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| 563system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits 564system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits 565system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits 566system.l2cache.demand_hits::total 4 # number of demand (read+write) hits 567system.l2cache.overall_hits::cpu.inst 4 # number of overall hits 568system.l2cache.overall_hits::total 4 # number of overall hits 569system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 570system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency 667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency 668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency 669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency 670system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency 671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency 672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency 673system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency | 573system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits 574system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits 575system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits 576system.l2cache.demand_hits::total 4 # number of demand (read+write) hits 577system.l2cache.overall_hits::cpu.inst 4 # number of overall hits 578system.l2cache.overall_hits::total 4 # number of overall hits 579system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 580system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 676system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency 677system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency 678system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency 679system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency 680system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency 681system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency 682system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency 683system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency |
| 684system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states |
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| 674system.membus.trans_dist::ReadResp 380 # Transaction distribution 675system.membus.trans_dist::ReadExReq 50 # Transaction distribution 676system.membus.trans_dist::ReadExResp 50 # Transaction distribution 677system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 678system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes) 679system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 680system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes) 681system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 685system.membus.trans_dist::ReadResp 380 # Transaction distribution 686system.membus.trans_dist::ReadExReq 50 # Transaction distribution 687system.membus.trans_dist::ReadExResp 50 # Transaction distribution 688system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 689system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes) 690system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 691system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes) 692system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |