3,5c3,5
< sim_seconds 0.000059 # Number of seconds simulated
< sim_ticks 59115000 # Number of ticks simulated
< final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000062 # Number of seconds simulated
> sim_ticks 62333000 # Number of ticks simulated
> final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 219311 # Simulator instruction rate (inst/s)
< host_op_rate 219196 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2295881155 # Simulator tick rate (ticks/s)
< host_mem_usage 637060 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 499257 # Simulator instruction rate (inst/s)
> host_op_rate 498740 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5505866075 # Simulator tick rate (ticks/s)
> host_mem_usage 635976 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 58984000 # Total gap between requests
---
> system.mem_ctrl.totGap 62196000 # Total gap between requests
190,204c190,205
< system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst
208,209c209,210
< system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s
211c212
< system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads
219c220
< system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads
221c222
< system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads
223,227c224,228
< system.mem_ctrl.avgGap 137172.09 # Average gap between requests
< system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 144641.86 # Average gap between requests
> system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ)
229,241c230,247
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states
> system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ)
243,253c249,264
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
273,274c284,285
< system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 59115 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 62333 # number of cpu cycles simulated
293c304
< system.cpu.num_busy_cycles 59115 # Number of busy cycles
---
> system.cpu.num_busy_cycles 62333 # Number of busy cycles
332c343
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
334c345
< system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use
339,341c350,352
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy
348c359
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
365,372c376,383
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles
389,396c400,407
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency
411,418c422,429
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles
427,435c438,446
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
437c448
< system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use
442,444c453,455
< system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy
446,447c457,458
< system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
451c462
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
464,469c475,480
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles
482,487c493,498
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency
500,505c511,516
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles
512,517c523,528
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
524c535
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
550c561
< system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
---
> system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
552c563
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
555c566
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
557c568
< system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use
562,566c573,577
< system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy
568,569c579,580
< system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
573c584
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
591,601c602,612
< system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles
624,634c635,645
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency
652,662c663,673
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles
674,684c685,695
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
691c702
< system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
714,715c725,726
< system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.9 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
< sim_seconds 0.000059 # Number of seconds simulated
< sim_ticks 59115000 # Number of ticks simulated
< final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000062 # Number of seconds simulated
> sim_ticks 62333000 # Number of ticks simulated
> final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 219311 # Simulator instruction rate (inst/s)
< host_op_rate 219196 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2295881155 # Simulator tick rate (ticks/s)
< host_mem_usage 637060 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 499257 # Simulator instruction rate (inst/s)
> host_op_rate 498740 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5505866075 # Simulator tick rate (ticks/s)
> host_mem_usage 635976 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 58984000 # Total gap between requests
---
> system.mem_ctrl.totGap 62196000 # Total gap between requests
190,204c190,205
< system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst
208,209c209,210
< system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s
211c212
< system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads
219c220
< system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads
221c222
< system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads
223,227c224,228
< system.mem_ctrl.avgGap 137172.09 # Average gap between requests
< system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 144641.86 # Average gap between requests
> system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ)
229,241c230,247
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states
> system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ)
243,253c249,264
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
273,274c284,285
< system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 59115 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 62333 # number of cpu cycles simulated
293c304
< system.cpu.num_busy_cycles 59115 # Number of busy cycles
---
> system.cpu.num_busy_cycles 62333 # Number of busy cycles
332c343
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
334c345
< system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use
339,341c350,352
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy
348c359
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
365,372c376,383
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles
389,396c400,407
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency
411,418c422,429
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles
427,435c438,446
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
437c448
< system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use
442,444c453,455
< system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy
446,447c457,458
< system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
451c462
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
464,469c475,480
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles
482,487c493,498
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency
500,505c511,516
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles
512,517c523,528
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
524c535
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
550c561
< system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
---
> system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
552c563
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
555c566
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
557c568
< system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use
562,566c573,577
< system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy
568,569c579,580
< system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
573c584
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
591,601c602,612
< system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles
624,634c635,645
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency
652,662c663,673
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles
674,684c685,695
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
691c702
< system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
714,715c725,726
< system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.9 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.7 # Layer utilization (%)