4,5c4,5
< sim_ticks 58892000 # Number of ticks simulated
< final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 59115000 # Number of ticks simulated
> final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 557970 # Simulator instruction rate (inst/s)
< host_op_rate 557350 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5812791438 # Simulator tick rate (ticks/s)
< host_mem_usage 633704 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 219311 # Simulator instruction rate (inst/s)
> host_op_rate 219196 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2295881155 # Simulator tick rate (ticks/s)
> host_mem_usage 637060 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 58762000 # Total gap between requests
---
> system.mem_ctrl.totGap 58984000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads
223,224c223,224
< system.mem_ctrl.avgGap 136655.81 # Average gap between requests
< system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined
---
> system.mem_ctrl.avgGap 137172.09 # Average gap between requests
> system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined
227c227
< system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states
237c237
< system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states
239,240c239,240
< system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ)
244,248c244,248
< system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states
251c251
< system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states
253c253
< system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
273,274c273,274
< system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 58892 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 59115 # number of cpu cycles simulated
293c293
< system.cpu.num_busy_cycles 58892 # Number of busy cycles
---
> system.cpu.num_busy_cycles 59115 # Number of busy cycles
332c332
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
334c334
< system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use
339,341c339,341
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy
348c348
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
365,372c365,372
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles
389,396c389,396
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency
411,418c411,418
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles
427,435c427,435
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
437c437
< system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use
442,444c442,444
< system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy
446,447c446,447
< system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id
451c451
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
464,469c464,469
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles
482,487c482,487
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency
500,505c500,505
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles
512,517c512,517
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
524c524
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
555c555
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
557c557
< system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use
559,560c559,560
< system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks.
562,570c562,570
< system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id
573c573
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
591,601c591,601
< system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles
624,634c624,634
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency
652,662c652,662
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles
674,685c674,691
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
708c714
< system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks)
< sim_ticks 58892000 # Number of ticks simulated
< final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 59115000 # Number of ticks simulated
> final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 557970 # Simulator instruction rate (inst/s)
< host_op_rate 557350 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5812791438 # Simulator tick rate (ticks/s)
< host_mem_usage 633704 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 219311 # Simulator instruction rate (inst/s)
> host_op_rate 219196 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2295881155 # Simulator tick rate (ticks/s)
> host_mem_usage 637060 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 58762000 # Total gap between requests
---
> system.mem_ctrl.totGap 58984000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads
223,224c223,224
< system.mem_ctrl.avgGap 136655.81 # Average gap between requests
< system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined
---
> system.mem_ctrl.avgGap 137172.09 # Average gap between requests
> system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined
227c227
< system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states
237c237
< system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states
239,240c239,240
< system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ)
---
> system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ)
244,248c244,248
< system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states
251c251
< system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states
253c253
< system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
273,274c273,274
< system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 58892 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 59115 # number of cpu cycles simulated
293c293
< system.cpu.num_busy_cycles 58892 # Number of busy cycles
---
> system.cpu.num_busy_cycles 59115 # Number of busy cycles
332c332
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
334c334
< system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use
339,341c339,341
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy
348c348
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
365,372c365,372
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles
389,396c389,396
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency
411,418c411,418
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles
427,435c427,435
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
437c437
< system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use
442,444c442,444
< system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy
446,447c446,447
< system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id
451c451
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
464,469c464,469
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles
482,487c482,487
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency
500,505c500,505
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles
512,517c512,517
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
524c524
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
555c555
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
557c557
< system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use
559,560c559,560
< system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks.
562,570c562,570
< system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id
573c573
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
591,601c591,601
< system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles
624,634c624,634
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency
652,662c652,662
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles
674,685c674,691
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states
708c714
< system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks)