Cross Reference: /gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000059 # Number of seconds simulated

4sim_ticks 58892000 # Number of ticks simulated
5final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 59115000 # Number of ticks simulated
5final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 557970 # Simulator instruction rate (inst/s)
8host_op_rate 557350 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5812791438 # Simulator tick rate (ticks/s)
10host_mem_usage 633704 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host

7host_inst_rate 219311 # Simulator instruction rate (inst/s)
8host_op_rate 219196 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2295881155 # Simulator tick rate (ticks/s)
10host_mem_usage 637060 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host

12sim_insts 5641 # Number of instructions simulated
13sim_ops 5641 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

17system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
19system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
20system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
21system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
22system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
23system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory
24system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory

25system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s)
28system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s)
29system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s)
30system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s)
32system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s)

25system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s)
28system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s)
29system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s)
30system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s)
32system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s)

33system.mem_ctrl.readReqs 430 # Number of read requests accepted
34system.mem_ctrl.writeReqs 0 # Number of write requests accepted
35system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue
36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.mem_ctrl.bytesReadDRAM 27520 # Total number of bytes read from DRAM
38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM
40system.mem_ctrl.bytesReadSys 27520 # Total read bytes from the system interface side
41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.mem_ctrl.perBankRdBursts::0 25 # Per bank write bursts
46system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts
47system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts
48system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts
49system.mem_ctrl.perBankRdBursts::4 6 # Per bank write bursts
50system.mem_ctrl.perBankRdBursts::5 3 # Per bank write bursts
51system.mem_ctrl.perBankRdBursts::6 11 # Per bank write bursts
52system.mem_ctrl.perBankRdBursts::7 49 # Per bank write bursts
53system.mem_ctrl.perBankRdBursts::8 53 # Per bank write bursts
54system.mem_ctrl.perBankRdBursts::9 74 # Per bank write bursts
55system.mem_ctrl.perBankRdBursts::10 34 # Per bank write bursts
56system.mem_ctrl.perBankRdBursts::11 19 # Per bank write bursts
57system.mem_ctrl.perBankRdBursts::12 50 # Per bank write bursts
58system.mem_ctrl.perBankRdBursts::13 27 # Per bank write bursts
59system.mem_ctrl.perBankRdBursts::14 72 # Per bank write bursts
60system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts
61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts
76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry

79system.mem_ctrl.totGap 58762000 # Total gap between requests

79system.mem_ctrl.totGap 58984000 # Total gap between requests

80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
86system.mem_ctrl.readPktSize::6 430 # Read request sizes (log2)
87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2)
88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2)
90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
94system.mem_ctrl.rdQLenPdf::0 430 # What read queue length does an incoming req see
95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see

190system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
191system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation
192system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation
193system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation
194system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
195system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation
196system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation
197system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation
198system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation
199system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation
200system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
202system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
203system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
204system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM

190system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation
191system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation
192system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation
193system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation
194system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation
195system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation
196system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation
197system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation
198system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation
199system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation
200system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation
201system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation
202system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation
203system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing
204system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM

205system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers

206system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst

206system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst

207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst

208system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
209system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s

208system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst
209system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s

210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

211system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s

211system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s

212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s

214system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage
215system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads

214system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage
215system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads

216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing

219system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads

219system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads

220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes

221system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads

221system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads

222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes

223system.mem_ctrl.avgGap 136655.81 # Average gap between requests
224system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined

223system.mem_ctrl.avgGap 137172.09 # Average gap between requests
224system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined

225system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
226system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)

227system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ)

227system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ)

228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)

230system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ)
231system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ)
232system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ)
233system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW)
234system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states

230system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ)
231system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ)
232system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ)
233system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW)
234system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states

235system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states

237system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states

237system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states

238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states

239system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ)
240system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ)

239system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ)
240system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ)

241system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ)
242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)

244system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ)
245system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ)
246system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ)
247system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW)
248system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states

244system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ)
245system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ)
246system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ)
247system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW)
248system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states

249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states

251system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states

251system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states

252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states

253system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

253system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

254system.cpu.dtb.read_hits 0 # DTB read hits
255system.cpu.dtb.read_misses 0 # DTB read misses
256system.cpu.dtb.read_accesses 0 # DTB read accesses
257system.cpu.dtb.write_hits 0 # DTB write hits
258system.cpu.dtb.write_misses 0 # DTB write misses
259system.cpu.dtb.write_accesses 0 # DTB write accesses
260system.cpu.dtb.hits 0 # DTB hits
261system.cpu.dtb.misses 0 # DTB misses
262system.cpu.dtb.accesses 0 # DTB accesses
263system.cpu.itb.read_hits 0 # DTB read hits
264system.cpu.itb.read_misses 0 # DTB read misses
265system.cpu.itb.read_accesses 0 # DTB read accesses
266system.cpu.itb.write_hits 0 # DTB write hits
267system.cpu.itb.write_misses 0 # DTB write misses
268system.cpu.itb.write_accesses 0 # DTB write accesses
269system.cpu.itb.hits 0 # DTB hits
270system.cpu.itb.misses 0 # DTB misses
271system.cpu.itb.accesses 0 # DTB accesses
272system.cpu.workload.num_syscalls 7 # Number of system calls

273system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states
274system.cpu.numCycles 58892 # number of cpu cycles simulated

273system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states
274system.cpu.numCycles 59115 # number of cpu cycles simulated

275system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
276system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
277system.cpu.committedInsts 5641 # Number of instructions committed
278system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
279system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
280system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
281system.cpu.num_func_calls 191 # number of times a function call or return occured
282system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
283system.cpu.num_int_insts 4957 # number of integer instructions
284system.cpu.num_fp_insts 2 # number of float instructions
285system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
286system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
287system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
288system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
289system.cpu.num_mem_refs 2037 # number of memory refs
290system.cpu.num_load_insts 1135 # Number of load instructions
291system.cpu.num_store_insts 902 # Number of store instructions
292system.cpu.num_idle_cycles 0 # Number of idle cycles

293system.cpu.num_busy_cycles 58892 # Number of busy cycles

293system.cpu.num_busy_cycles 59115 # Number of busy cycles

294system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
295system.cpu.idle_fraction 0 # Percentage of idle cycles
296system.cpu.Branches 886 # Number of branches fetched
297system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
298system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
299system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
300system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
301system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
302system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
303system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
304system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
305system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
306system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
307system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
308system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
309system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
310system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
311system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
312system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
313system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
314system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
315system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
316system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
317system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
318system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
319system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
320system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
321system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
322system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
323system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
324system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
325system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
326system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
327system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
328system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
329system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
330system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
331system.cpu.op_class::total 5642 # Class of executed instruction

332system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

332system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

333system.cpu.dcache.tags.replacements 0 # number of replacements

334system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use

334system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use

335system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
336system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
337system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
338system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

339system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
340system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
341system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy

339system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor
340system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy
341system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy

342system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
343system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
344system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
345system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
346system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
347system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses

348system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

348system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

349system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
350system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
351system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
352system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
353system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
354system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
355system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
356system.cpu.dcache.overall_hits::total 1899 # number of overall hits
357system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
358system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
359system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
360system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
361system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
362system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
363system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
364system.cpu.dcache.overall_misses::total 137 # number of overall misses

365system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles
366system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles
367system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles
368system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles
369system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles
370system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
371system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
372system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles

365system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles
366system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles
367system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles
368system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles
369system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles
370system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles
371system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles
372system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles

373system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
374system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
375system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
376system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
377system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
378system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
379system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
380system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
381system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
382system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
383system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
384system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
385system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
386system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
387system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
388system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses

389system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
390system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
391system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
392system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency
393system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
394system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency
395system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
396system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency

389system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency
390system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency
391system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency
392system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency
393system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
394system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency
395system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency
396system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency

397system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
398system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
399system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
400system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
401system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
402system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
403system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
404system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
405system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
406system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
407system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
408system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
409system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
410system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses

411system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles
412system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles
413system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles
414system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles
415system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles
416system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
417system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
418system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles

411system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles
412system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles
413system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles
414system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles
415system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles
416system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles
417system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles
418system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles

419system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
420system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
421system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
422system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
423system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
424system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
425system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
426system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses

427system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
428system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
429system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
430system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency
431system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
432system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
433system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
434system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
435system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

427system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency
428system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency
429system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency
430system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency
431system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
432system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
433system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency
434system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency
435system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

436system.cpu.icache.tags.replacements 94 # number of replacements

437system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use

437system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use

438system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
439system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
440system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
441system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

442system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
443system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
444system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy

442system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor
443system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy
444system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy

445system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id

446system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
447system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id

446system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
447system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id

448system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
449system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
450system.cpu.icache.tags.data_accesses 11583 # Number of data accesses

451system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

451system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

452system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
453system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
454system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
455system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
456system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
457system.cpu.icache.overall_hits::total 5346 # number of overall hits
458system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
459system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
460system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
461system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
462system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
463system.cpu.icache.overall_misses::total 297 # number of overall misses

464system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
465system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
466system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
467system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
468system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
469system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles

464system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles
465system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles
466system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles
467system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles
468system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles
469system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles

470system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
471system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
472system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
473system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
474system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
475system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
476system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
477system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
478system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
479system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
480system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
481system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses

482system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
483system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
484system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
485system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
486system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
487system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency

482system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency
483system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency
484system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
485system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency
486system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency
487system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency

488system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
489system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
490system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
491system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
492system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
493system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
494system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
495system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
496system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
497system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
498system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
499system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses

500system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
501system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
502system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
503system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
504system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
505system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles

500system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles
501system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles
502system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles
503system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles
504system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles
505system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles

506system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
507system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
508system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
509system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
510system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
511system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses

512system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
513system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
514system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
515system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
516system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
517system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency

512system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency
513system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency
514system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
515system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency
516system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency
517system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency

518system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
519system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
520system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
521system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
522system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
523system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

524system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

524system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

525system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
526system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
527system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution
528system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution
529system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution
530system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
531system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
532system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
533system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 19008 # Cumulative packet size per connected master and slave (bytes)
534system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
535system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes)
536system.l2bus.snoops 0 # Total snoops (count)
537system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes)
538system.l2bus.snoop_fanout::samples 434 # Request fanout histogram
539system.l2bus.snoop_fanout::mean 0 # Request fanout histogram
540system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
541system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
542system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram
543system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
544system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
545system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
546system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
547system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram
548system.l2bus.snoop_fanout::total 434 # Request fanout histogram
549system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks)
550system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
551system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks)
552system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
553system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
554system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)

555system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

555system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

556system.l2cache.tags.replacements 0 # number of replacements

557system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use

557system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use

558system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.

559system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
560system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.

559system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
560system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks.

561system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

562system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
563system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
564system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
565system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
566system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
567system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
568system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
569system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
570system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id

562system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor
563system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor
564system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy
565system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy
566system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy
567system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
568system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
569system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
570system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id

571system.l2cache.tags.tag_accesses 4654 # Number of tag accesses
572system.l2cache.tags.data_accesses 4654 # Number of data accesses

573system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

573system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

574system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits
575system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits
576system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
577system.l2cache.demand_hits::total 4 # number of demand (read+write) hits
578system.l2cache.overall_hits::cpu.inst 4 # number of overall hits
579system.l2cache.overall_hits::total 4 # number of overall hits
580system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
581system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
582system.l2cache.ReadSharedReq_misses::cpu.inst 293 # number of ReadSharedReq misses
583system.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses
584system.l2cache.ReadSharedReq_misses::total 380 # number of ReadSharedReq misses
585system.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses
586system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses
587system.l2cache.demand_misses::total 430 # number of demand (read+write) misses
588system.l2cache.overall_misses::cpu.inst 293 # number of overall misses
589system.l2cache.overall_misses::cpu.data 137 # number of overall misses
590system.l2cache.overall_misses::total 430 # number of overall misses

591system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
592system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
593system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
594system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
595system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
596system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
597system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
598system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
599system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
600system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
601system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles

591system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles
592system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles
593system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles
594system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles
595system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles
596system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles
597system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles
598system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles
599system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles
600system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles
601system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles

602system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
603system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
604system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
605system.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses)
606system.l2cache.ReadSharedReq_accesses::total 384 # number of ReadSharedReq accesses(hits+misses)
607system.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
608system.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses
609system.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses
610system.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
611system.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses
612system.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses
613system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
614system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
615system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.986532 # miss rate for ReadSharedReq accesses
616system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
617system.l2cache.ReadSharedReq_miss_rate::total 0.989583 # miss rate for ReadSharedReq accesses
618system.l2cache.demand_miss_rate::cpu.inst 0.986532 # miss rate for demand accesses
619system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
620system.l2cache.demand_miss_rate::total 0.990783 # miss rate for demand accesses
621system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses
622system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
623system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses

624system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
625system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
626system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
627system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
628system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
629system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
630system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
631system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
632system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
633system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
634system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency

624system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency
625system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency
626system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency
627system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency
628system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency
629system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
630system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
631system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency
632system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency
633system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency
634system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency

635system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
636system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
637system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
638system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
639system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
640system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
641system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
642system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
643system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses
644system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
645system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses
646system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
647system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
648system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
649system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
650system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
651system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses

652system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
653system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
654system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
655system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
656system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
657system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
658system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
659system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
660system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
661system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
662system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles

652system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles
653system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles
654system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles
655system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles
656system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles
657system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles
658system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles
659system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles
660system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles
661system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles
662system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles

663system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
664system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
665system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
666system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
667system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989583 # mshr miss rate for ReadSharedReq accesses
668system.l2cache.demand_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for demand accesses
669system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
670system.l2cache.demand_mshr_miss_rate::total 0.990783 # mshr miss rate for demand accesses
671system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses
672system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
673system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses

674system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
675system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
676system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
677system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
678system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
679system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
680system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
681system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
682system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
683system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
684system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
685system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states

674system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency
675system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency
676system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency
677system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency
678system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency
679system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
680system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
681system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
682system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency
683system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency
684system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency
685system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
686system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
687system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
688system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
689system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
690system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
691system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states

686system.membus.trans_dist::ReadResp 380 # Transaction distribution
687system.membus.trans_dist::ReadExReq 50 # Transaction distribution
688system.membus.trans_dist::ReadExResp 50 # Transaction distribution
689system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
690system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
691system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
692system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
693system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
694system.membus.snoops 0 # Total snoops (count)
695system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
696system.membus.snoop_fanout::samples 430 # Request fanout histogram
697system.membus.snoop_fanout::mean 0 # Request fanout histogram
698system.membus.snoop_fanout::stdev 0 # Request fanout histogram
699system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
700system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
701system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
702system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
703system.membus.snoop_fanout::min_value 0 # Request fanout histogram
704system.membus.snoop_fanout::max_value 0 # Request fanout histogram
705system.membus.snoop_fanout::total 430 # Request fanout histogram
706system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
707system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)

692system.membus.trans_dist::ReadResp 380 # Transaction distribution
693system.membus.trans_dist::ReadExReq 50 # Transaction distribution
694system.membus.trans_dist::ReadExResp 50 # Transaction distribution
695system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
696system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
697system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
698system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
699system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
700system.membus.snoops 0 # Total snoops (count)
701system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
702system.membus.snoop_fanout::samples 430 # Request fanout histogram
703system.membus.snoop_fanout::mean 0 # Request fanout histogram
704system.membus.snoop_fanout::stdev 0 # Request fanout histogram
705system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
706system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
707system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
708system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
709system.membus.snoop_fanout::min_value 0 # Request fanout histogram
710system.membus.snoop_fanout::max_value 0 # Request fanout histogram
711system.membus.snoop_fanout::total 430 # Request fanout histogram
712system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
713system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)

708system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks)

714system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks)