1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000059 # Number of seconds simulated
4sim_ticks 58892000 # Number of ticks simulated
5final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 350541 # Simulator instruction rate (inst/s)
8host_op_rate 350101 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3650563038 # Simulator tick rate (ticks/s)
10host_mem_usage 636120 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 5641 # Number of instructions simulated
13sim_ops 5641 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
19system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
--- 370 unchanged lines hidden (view full) ---
390system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
391system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency
392system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
393system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
394system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
395system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
396system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
397system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
398system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
399system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
400system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
401system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
402system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
403system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
404system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
405system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
422system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
423system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
424system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
425system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency
426system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
427system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
428system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
429system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
430system.cpu.icache.tags.replacements 94 # number of replacements
431system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
432system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
433system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
434system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
435system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
437system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
479system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
480system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
481system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
482system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
483system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
484system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
485system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
486system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
487system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
488system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
489system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
490system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
491system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
492system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
493system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
494system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
--- 8 unchanged lines hidden (view full) ---
503system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
504system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
505system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
506system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
507system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
508system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
509system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
510system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
511system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
512system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
513system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
514system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
515system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
516system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
517system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
518system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
--- 103 unchanged lines hidden (view full) ---
622system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
623system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
624system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
625system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
626system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
627system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
628system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
629system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
630system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
631system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
632system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses
633system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
634system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses
635system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
636system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
637system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
--- 28 unchanged lines hidden (view full) ---
666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
670system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
673system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
674system.membus.trans_dist::ReadResp 380 # Transaction distribution
675system.membus.trans_dist::ReadExReq 50 # Transaction distribution
676system.membus.trans_dist::ReadExResp 50 # Transaction distribution
677system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
678system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
679system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
680system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
681system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
--- 17 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000059 # Number of seconds simulated
4sim_ticks 58892000 # Number of ticks simulated
5final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 350541 # Simulator instruction rate (inst/s)
8host_op_rate 350101 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3650563038 # Simulator tick rate (ticks/s)
10host_mem_usage 636120 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 5641 # Number of instructions simulated
13sim_ops 5641 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
19system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
--- 370 unchanged lines hidden (view full) ---
390system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency
391system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency
392system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
393system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
394system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
395system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
396system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
397system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
398system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
399system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
400system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
401system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
402system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
403system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
404system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
405system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
422system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
423system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
424system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
425system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency
426system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
427system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
428system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
429system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
430system.cpu.icache.tags.replacements 94 # number of replacements
431system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
432system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
433system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
434system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
435system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
437system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
479system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
480system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
481system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
482system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
483system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
484system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
485system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
486system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
487system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
488system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
489system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
490system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
491system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
492system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
493system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
494system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
--- 8 unchanged lines hidden (view full) ---
503system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
504system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
505system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
506system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
507system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
508system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
509system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
510system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
511system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
512system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
513system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
514system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
515system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
516system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
517system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
518system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
--- 103 unchanged lines hidden (view full) ---
622system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
623system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
624system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
625system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
626system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
627system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
628system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
629system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
630system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
631system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
632system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses
633system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
634system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses
635system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
636system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
637system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
--- 28 unchanged lines hidden (view full) ---
666system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
667system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
668system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
669system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
670system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
671system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
672system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
673system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
674system.membus.trans_dist::ReadResp 380 # Transaction distribution
675system.membus.trans_dist::ReadExReq 50 # Transaction distribution
676system.membus.trans_dist::ReadExResp 50 # Transaction distribution
677system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
678system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
679system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
680system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
681system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
--- 17 unchanged lines hidden ---