| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
| 26mem_ranges=0:536870911 | 26mem_ranges=0:536870911:0:0:0:0 |
| 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags | 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags |
| 103addr_ranges=0:18446744073709551615 | 103addr_ranges=0:18446744073709551615:0:0:0:0 |
| 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=MipsTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags | 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=MipsTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags |
| 154addr_ranges=0:18446744073709551615 | 154addr_ranges=0:18446744073709551615:0:0:0:0 |
| 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 109 unchanged lines hidden (view full) --- 272eventq_index=0 273lookup_latency=0 274max_capacity=8388608 275system=system 276 277[system.l2cache] 278type=Cache 279children=tags | 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 109 unchanged lines hidden (view full) --- 272eventq_index=0 273lookup_latency=0 274max_capacity=8388608 275system=system 276 277[system.l2cache] 278type=Cache 279children=tags |
| 280addr_ranges=0:18446744073709551615 | 280addr_ranges=0:18446744073709551615:0:0:0:0 |
| 281assoc=8 282clk_domain=system.clk_domain 283clusivity=mostly_incl 284default_p_state=UNDEFINED 285demand_mshr_reserve=1 286eventq_index=0 287hit_latency=20 288is_read_only=false --- 28 unchanged lines hidden (view full) --- 317p_state_clk_gate_max=1000000000000 318p_state_clk_gate_min=1000 319power_model=Null 320sequential_access=false 321size=262144 322 323[system.mem_ctrl] 324type=DRAMCtrl | 281assoc=8 282clk_domain=system.clk_domain 283clusivity=mostly_incl 284default_p_state=UNDEFINED 285demand_mshr_reserve=1 286eventq_index=0 287hit_latency=20 288is_read_only=false --- 28 unchanged lines hidden (view full) --- 317p_state_clk_gate_max=1000000000000 318p_state_clk_gate_min=1000 319power_model=Null 320sequential_access=false 321size=262144 322 323[system.mem_ctrl] 324type=DRAMCtrl |
| 325IDD0=0.075000 | 325IDD0=0.055000 |
| 326IDD02=0.000000 | 326IDD02=0.000000 |
| 327IDD2N=0.050000 | 327IDD2N=0.032000 |
| 328IDD2N2=0.000000 329IDD2P0=0.000000 330IDD2P02=0.000000 | 328IDD2N2=0.000000 329IDD2P0=0.000000 330IDD2P02=0.000000 |
| 331IDD2P1=0.000000 | 331IDD2P1=0.032000 |
| 332IDD2P12=0.000000 | 332IDD2P12=0.000000 |
| 333IDD3N=0.057000 | 333IDD3N=0.038000 |
| 334IDD3N2=0.000000 335IDD3P0=0.000000 336IDD3P02=0.000000 | 334IDD3N2=0.000000 335IDD3P0=0.000000 336IDD3P02=0.000000 |
| 337IDD3P1=0.000000 | 337IDD3P1=0.038000 |
| 338IDD3P12=0.000000 | 338IDD3P12=0.000000 |
| 339IDD4R=0.187000 | 339IDD4R=0.157000 |
| 340IDD4R2=0.000000 | 340IDD4R2=0.000000 |
| 341IDD4W=0.165000 | 341IDD4W=0.125000 |
| 342IDD4W2=0.000000 | 342IDD4W2=0.000000 |
| 343IDD5=0.220000 | 343IDD5=0.235000 |
| 344IDD52=0.000000 | 344IDD52=0.000000 |
| 345IDD6=0.000000 | 345IDD6=0.020000 |
| 346IDD62=0.000000 347VDD=1.500000 348VDD2=0.000000 349activation_limit=4 350addr_mapping=RoRaBaCoCh 351bank_groups_per_rank=0 352banks_per_rank=8 353burst_length=8 354channels=1 355clk_domain=system.clk_domain 356conf_table_reported=true 357default_p_state=UNDEFINED 358device_bus_width=8 359device_rowbuffer_size=1024 360device_size=536870912 361devices_per_rank=8 362dll=true 363eventq_index=0 364in_addr_map=true | 346IDD62=0.000000 347VDD=1.500000 348VDD2=0.000000 349activation_limit=4 350addr_mapping=RoRaBaCoCh 351bank_groups_per_rank=0 352banks_per_rank=8 353burst_length=8 354channels=1 355clk_domain=system.clk_domain 356conf_table_reported=true 357default_p_state=UNDEFINED 358device_bus_width=8 359device_rowbuffer_size=1024 360device_size=536870912 361devices_per_rank=8 362dll=true 363eventq_index=0 364in_addr_map=true |
| 365kvm_map=true |
|
| 365max_accesses_per_row=16 366mem_sched_policy=frfcfs 367min_writes_per_switch=16 368null=false 369p_state_clk_gate_bins=20 370p_state_clk_gate_max=1000000000000 371p_state_clk_gate_min=1000 372page_policy=open_adaptive 373power_model=Null | 366max_accesses_per_row=16 367mem_sched_policy=frfcfs 368min_writes_per_switch=16 369null=false 370p_state_clk_gate_bins=20 371p_state_clk_gate_max=1000000000000 372p_state_clk_gate_min=1000 373page_policy=open_adaptive 374power_model=Null |
| 374range=0:536870911 | 375range=0:536870911:0:0:0:0 |
| 375ranks_per_channel=2 376read_buffer_size=32 377static_backend_latency=10000 378static_frontend_latency=10000 379tBURST=5000 380tCCD_L=0 381tCK=1250 382tCL=13750 --- 5 unchanged lines hidden (view full) --- 388tRP=13750 389tRRD=6000 390tRRD_L=0 391tRTP=7500 392tRTW=2500 393tWR=15000 394tWTR=7500 395tXAW=30000 | 376ranks_per_channel=2 377read_buffer_size=32 378static_backend_latency=10000 379static_frontend_latency=10000 380tBURST=5000 381tCCD_L=0 382tCK=1250 383tCL=13750 --- 5 unchanged lines hidden (view full) --- 389tRP=13750 390tRRD=6000 391tRRD_L=0 392tRTP=7500 393tRTW=2500 394tWR=15000 395tWTR=7500 396tXAW=30000 |
| 396tXP=0 | 397tXP=6000 |
| 397tXPDLL=0 | 398tXPDLL=0 |
| 398tXS=0 | 399tXS=270000 |
| 399tXSDLL=0 400write_buffer_size=64 401write_high_thresh_perc=85 402write_low_thresh_perc=50 403port=system.membus.master[0] 404 405[system.membus] 406type=CoherentXBar | 400tXSDLL=0 401write_buffer_size=64 402write_high_thresh_perc=85 403write_low_thresh_perc=50 404port=system.membus.master[0] 405 406[system.membus] 407type=CoherentXBar |
| 408children=snoop_filter |
|
| 407clk_domain=system.clk_domain 408default_p_state=UNDEFINED 409eventq_index=0 410forward_latency=4 411frontend_latency=3 412p_state_clk_gate_bins=20 413p_state_clk_gate_max=1000000000000 414p_state_clk_gate_min=1000 415point_of_coherency=true 416power_model=Null 417response_latency=2 | 409clk_domain=system.clk_domain 410default_p_state=UNDEFINED 411eventq_index=0 412forward_latency=4 413frontend_latency=3 414p_state_clk_gate_bins=20 415p_state_clk_gate_max=1000000000000 416p_state_clk_gate_min=1000 417point_of_coherency=true 418power_model=Null 419response_latency=2 |
| 418snoop_filter=Null | 420snoop_filter=system.membus.snoop_filter |
| 419snoop_response_latency=4 420system=system 421use_default_range=false 422width=16 423master=system.mem_ctrl.port 424slave=system.l2cache.mem_side system.system_port 425 | 421snoop_response_latency=4 422system=system 423use_default_range=false 424width=16 425master=system.mem_ctrl.port 426slave=system.l2cache.mem_side system.system_port 427 |
| 428[system.membus.snoop_filter] 429type=SnoopFilter 430eventq_index=0 431lookup_latency=1 432max_capacity=8388608 433system=system 434 |
|