1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
26mem_ranges=0:536870911:0:0:0:0 |
27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 115 unchanged lines hidden (view full) --- 150domains= 151enable=false 152eventq_index=0 153sys_clk_domain=system.clk_domain 154transition_latency=100000000 155 156[system.mem_ctrl] 157type=DRAMCtrl |
158IDD0=0.055000 |
159IDD02=0.000000 |
160IDD2N=0.032000 |
161IDD2N2=0.000000 162IDD2P0=0.000000 163IDD2P02=0.000000 |
164IDD2P1=0.032000 |
165IDD2P12=0.000000 |
166IDD3N=0.038000 |
167IDD3N2=0.000000 168IDD3P0=0.000000 169IDD3P02=0.000000 |
170IDD3P1=0.038000 |
171IDD3P12=0.000000 |
172IDD4R=0.157000 |
173IDD4R2=0.000000 |
174IDD4W=0.125000 |
175IDD4W2=0.000000 |
176IDD5=0.235000 |
177IDD52=0.000000 |
178IDD6=0.020000 |
179IDD62=0.000000 180VDD=1.500000 181VDD2=0.000000 182activation_limit=4 183addr_mapping=RoRaBaCoCh 184bank_groups_per_rank=0 185banks_per_rank=8 186burst_length=8 187channels=1 188clk_domain=system.clk_domain 189conf_table_reported=true 190default_p_state=UNDEFINED 191device_bus_width=8 192device_rowbuffer_size=1024 193device_size=536870912 194devices_per_rank=8 195dll=true 196eventq_index=0 197in_addr_map=true |
198kvm_map=true |
199max_accesses_per_row=16 200mem_sched_policy=frfcfs 201min_writes_per_switch=16 202null=false 203p_state_clk_gate_bins=20 204p_state_clk_gate_max=1000000000000 205p_state_clk_gate_min=1000 206page_policy=open_adaptive 207power_model=Null |
208range=0:536870911:0:0:0:0 |
209ranks_per_channel=2 210read_buffer_size=32 211static_backend_latency=10000 212static_frontend_latency=10000 213tBURST=5000 214tCCD_L=0 215tCK=1250 216tCL=13750 --- 5 unchanged lines hidden (view full) --- 222tRP=13750 223tRRD=6000 224tRRD_L=0 225tRTP=7500 226tRTW=2500 227tWR=15000 228tWTR=7500 229tXAW=30000 |
230tXP=6000 |
231tXPDLL=0 |
232tXS=270000 |
233tXSDLL=0 234write_buffer_size=64 235write_high_thresh_perc=85 236write_low_thresh_perc=50 237port=system.membus.master[0] 238 239[system.membus] 240type=CoherentXBar |
241children=snoop_filter |
242clk_domain=system.clk_domain 243default_p_state=UNDEFINED 244eventq_index=0 245forward_latency=4 246frontend_latency=3 247p_state_clk_gate_bins=20 248p_state_clk_gate_max=1000000000000 249p_state_clk_gate_min=1000 250point_of_coherency=true 251power_model=Null 252response_latency=2 |
253snoop_filter=system.membus.snoop_filter |
254snoop_response_latency=4 255system=system 256use_default_range=false 257width=16 258master=system.mem_ctrl.port 259slave=system.cpu.icache_port system.cpu.dcache_port system.system_port 260 |
261[system.membus.snoop_filter] 262type=SnoopFilter 263eventq_index=0 264lookup_latency=1 265max_capacity=8388608 266system=system 267 |