1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=0:536870911
27memories=system.mem_ctrl
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null

--- 115 unchanged lines hidden (view full) ---

150domains=
151enable=false
152eventq_index=0
153sys_clk_domain=system.clk_domain
154transition_latency=100000000
155
156[system.mem_ctrl]
157type=DRAMCtrl
158IDD0=0.075000
159IDD02=0.000000
160IDD2N=0.050000
161IDD2N2=0.000000
162IDD2P0=0.000000
163IDD2P02=0.000000
164IDD2P1=0.000000
165IDD2P12=0.000000
166IDD3N=0.057000
167IDD3N2=0.000000
168IDD3P0=0.000000
169IDD3P02=0.000000
170IDD3P1=0.000000
171IDD3P12=0.000000
172IDD4R=0.187000
173IDD4R2=0.000000
174IDD4W=0.165000
175IDD4W2=0.000000
176IDD5=0.220000
177IDD52=0.000000
178IDD6=0.000000
179IDD62=0.000000
180VDD=1.500000
181VDD2=0.000000
182activation_limit=4
183addr_mapping=RoRaBaCoCh
184bank_groups_per_rank=0
185banks_per_rank=8
186burst_length=8
187channels=1
188clk_domain=system.clk_domain
189conf_table_reported=true
190default_p_state=UNDEFINED
191device_bus_width=8
192device_rowbuffer_size=1024
193device_size=536870912
194devices_per_rank=8
195dll=true
196eventq_index=0
197in_addr_map=true
198max_accesses_per_row=16
199mem_sched_policy=frfcfs
200min_writes_per_switch=16
201null=false
202p_state_clk_gate_bins=20
203p_state_clk_gate_max=1000000000000
204p_state_clk_gate_min=1000
205page_policy=open_adaptive
206power_model=Null
207range=0:536870911
208ranks_per_channel=2
209read_buffer_size=32
210static_backend_latency=10000
211static_frontend_latency=10000
212tBURST=5000
213tCCD_L=0
214tCK=1250
215tCL=13750

--- 5 unchanged lines hidden (view full) ---

221tRP=13750
222tRRD=6000
223tRRD_L=0
224tRTP=7500
225tRTW=2500
226tWR=15000
227tWTR=7500
228tXAW=30000
229tXP=0
230tXPDLL=0
231tXS=0
232tXSDLL=0
233write_buffer_size=64
234write_high_thresh_perc=85
235write_low_thresh_perc=50
236port=system.membus.master[0]
237
238[system.membus]
239type=CoherentXBar
240clk_domain=system.clk_domain
241default_p_state=UNDEFINED
242eventq_index=0
243forward_latency=4
244frontend_latency=3
245p_state_clk_gate_bins=20
246p_state_clk_gate_max=1000000000000
247p_state_clk_gate_min=1000
248point_of_coherency=true
249power_model=Null
250response_latency=2
251snoop_filter=Null
252snoop_response_latency=4
253system=system
254use_default_range=false
255width=16
256master=system.mem_ctrl.port
257slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
258