| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated |
| 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 50074000 # Number of ticks simulated 5final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 256506 # Simulator instruction rate (inst/s) 8host_op_rate 296356 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2557788683 # Simulator tick rate (ticks/s) 10host_mem_usage 651420 # Number of bytes of host memory used | 7host_inst_rate 207988 # Simulator instruction rate (inst/s) 8host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2085706484 # Simulator tick rate (ticks/s) 10host_mem_usage 655032 # Number of bytes of host memory used |
| 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory |
| 25system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) |
| 33system.mem_ctrl.readReqs 351 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 33system.mem_ctrl.readReqs 351 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.mem_ctrl.totGap 49757000 # Total gap between requests | 79system.mem_ctrl.totGap 49975000 # Total gap between requests |
| 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation | 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation |
| 192system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation | 192system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation |
| 194system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation | 194system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation |
| 196system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation | 196system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation |
| 198system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation | 198system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation |
| 203system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM | 203system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers | 205system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers |
| 206system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst | 206system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst |
| 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s | 208system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s |
| 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s | 211system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s |
| 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads | 214system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads |
| 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.mem_ctrl.avgGap 141757.83 # Average gap between requests | 223system.mem_ctrl.avgGap 142378.92 # Average gap between requests |
| 224system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) | 224system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) |
| 227system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) | 227system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) |
| 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 230system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states | 230system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states |
| 235system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states | 237system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states |
| 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 244system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states | 244system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states |
| 249system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states | 251system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states |
| 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states 254system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 253system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states 254system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 255system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 260system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 261system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 262system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 276system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 277system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 278system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 279system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 280system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 281system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 282system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 283system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 255system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 260system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 261system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 262system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 276system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 277system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 278system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 279system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 280system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 281system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 282system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 283system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 284system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 284system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 285system.cpu.dtb.walker.walks 0 # Table walker walks requested 286system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 287system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 288system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 289system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 306system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.dtb.read_accesses 0 # DTB read accesses 309system.cpu.dtb.write_accesses 0 # DTB write accesses 310system.cpu.dtb.inst_accesses 0 # ITB inst accesses 311system.cpu.dtb.hits 0 # DTB hits 312system.cpu.dtb.misses 0 # DTB misses 313system.cpu.dtb.accesses 0 # DTB accesses | 285system.cpu.dtb.walker.walks 0 # Table walker walks requested 286system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 287system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 288system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 289system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 306system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.dtb.read_accesses 0 # DTB read accesses 309system.cpu.dtb.write_accesses 0 # DTB write accesses 310system.cpu.dtb.inst_accesses 0 # ITB inst accesses 311system.cpu.dtb.hits 0 # DTB hits 312system.cpu.dtb.misses 0 # DTB misses 313system.cpu.dtb.accesses 0 # DTB accesses |
| 314system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 314system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 315system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 336system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 315system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 336system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 344system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 344system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 345system.cpu.itb.walker.walks 0 # Table walker walks requested 346system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 367system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.itb.read_accesses 0 # DTB read accesses 369system.cpu.itb.write_accesses 0 # DTB write accesses 370system.cpu.itb.inst_accesses 0 # ITB inst accesses 371system.cpu.itb.hits 0 # DTB hits 372system.cpu.itb.misses 0 # DTB misses 373system.cpu.itb.accesses 0 # DTB accesses 374system.cpu.workload.num_syscalls 13 # Number of system calls | 345system.cpu.itb.walker.walks 0 # Table walker walks requested 346system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 367system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.itb.read_accesses 0 # DTB read accesses 369system.cpu.itb.write_accesses 0 # DTB write accesses 370system.cpu.itb.inst_accesses 0 # ITB inst accesses 371system.cpu.itb.hits 0 # DTB hits 372system.cpu.itb.misses 0 # DTB misses 373system.cpu.itb.accesses 0 # DTB accesses 374system.cpu.workload.num_syscalls 13 # Number of system calls |
| 375system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states 376system.cpu.numCycles 49855 # number of cpu cycles simulated | 375system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states 376system.cpu.numCycles 50074 # number of cpu cycles simulated |
| 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 4988 # Number of instructions committed 380system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 381system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 382system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 383system.cpu.num_func_calls 215 # number of times a function call or return occured 384system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 389system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 390system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 391system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 392system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 393system.cpu.num_mem_refs 2035 # number of memory refs 394system.cpu.num_load_insts 1085 # Number of load instructions 395system.cpu.num_store_insts 950 # Number of store instructions 396system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 4988 # Number of instructions committed 380system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 381system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 382system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 383system.cpu.num_func_calls 215 # number of times a function call or return occured 384system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 389system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 390system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 391system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 392system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 393system.cpu.num_mem_refs 2035 # number of memory refs 394system.cpu.num_load_insts 1085 # Number of load instructions 395system.cpu.num_store_insts 950 # Number of store instructions 396system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 397system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles | 397system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles |
| 398system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 399system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 400system.cpu.Branches 1107 # Number of branches fetched 401system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 402system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 403system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 404system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 405system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 428system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 429system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 430system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 431system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 432system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 433system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 434system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 435system.cpu.op_class::total 5831 # Class of executed instruction | 398system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 399system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 400system.cpu.Branches 1107 # Number of branches fetched 401system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 402system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 403system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 404system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 405system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 428system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 429system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 430system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 431system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 432system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 433system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 434system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 435system.cpu.op_class::total 5831 # Class of executed instruction |
| 436system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 436system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 437system.cpu.dcache.tags.replacements 0 # number of replacements | 437system.cpu.dcache.tags.replacements 0 # number of replacements |
| 438system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use | 438system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use |
| 439system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 440system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 441system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 442system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 439system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 440system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 441system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 442system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 443system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor 444system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy | 443system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor 444system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy |
| 446system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 450system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses | 446system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 450system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses |
| 452system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 452system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 453system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 454system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 455system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 456system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 457system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 458system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 459system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 460system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 465system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 466system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 467system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 468system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 469system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 470system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 471system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 472system.cpu.dcache.overall_misses::total 142 # number of overall misses | 453system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 454system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 455system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 456system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 457system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 458system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 459system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 460system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 465system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 466system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 467system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 468system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 469system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 470system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 471system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 472system.cpu.dcache.overall_misses::total 142 # number of overall misses |
| 473system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles 474system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles 477system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles 478system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles 479system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles 480system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles | 473system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles 474system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles 477system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles 478system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles 479system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles 480system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles |
| 481system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 486system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 493system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 495system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 497system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 498system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 499system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 500system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses | 481system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 486system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 493system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 495system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 497system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 498system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 499system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 500system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses |
| 501system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency 502system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency 503system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency 505system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 506system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency | 501system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency 502system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency 503system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency 505system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency 506system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency |
| 509system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 516system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 517system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 519system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 520system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 521system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 522system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 509system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 516system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 517system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 519system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 520system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 521system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 522system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles 524system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles | 523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles 524system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles |
| 531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 536system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 537system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 538system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses | 531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 536system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 537system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 538system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses |
| 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 547system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency 547system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 548system.cpu.icache.tags.replacements 70 # number of replacements | 548system.cpu.icache.tags.replacements 70 # number of replacements |
| 549system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use | 549system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use |
| 550system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 550system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 554system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy | 554system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy |
| 557system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id | 557system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id |
| 558system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id | 558system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id |
| 560system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 561system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 562system.cpu.icache.tags.data_accesses 10305 # Number of data accesses | 560system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 561system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 562system.cpu.icache.tags.data_accesses 10305 # Number of data accesses |
| 563system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 563system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 564system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 569system.cpu.icache.overall_hits::total 4779 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 575system.cpu.icache.overall_misses::total 249 # number of overall misses | 564system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 569system.cpu.icache.overall_hits::total 4779 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 575system.cpu.icache.overall_misses::total 249 # number of overall misses |
| 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles | 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles |
| 582system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses | 582system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses |
| 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency | 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency |
| 600system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 607system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 608system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 609system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 610system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 611system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses | 600system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 607system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 608system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 609system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 610system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 611system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses |
| 612system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles 613system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles 614system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles 615system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles 616system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles 617system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles | 612system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles 613system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles 614system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles 615system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles 616system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles 617system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles |
| 618system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 620system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 621system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 623system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses | 618system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 620system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 621system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 623system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses |
| 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency 625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 627system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency | 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency 625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency 627system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency |
| 630system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 631system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 632system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 633system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 634system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 635system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 630system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 631system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 632system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 633system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 634system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 635system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 636system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 636system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 637system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 638system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 639system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 640system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 641system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 642system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 643system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 644system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 659system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 660system.l2bus.snoop_fanout::total 391 # Request fanout histogram 661system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 662system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 663system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 664system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 665system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 666system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) | 637system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 638system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 639system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 640system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 641system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 642system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 643system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 644system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 659system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 660system.l2bus.snoop_fanout::total 391 # Request fanout histogram 661system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 662system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 663system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 664system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 665system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 666system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 667system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 667system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 668system.l2cache.tags.replacements 0 # number of replacements | 668system.l2cache.tags.replacements 0 # number of replacements |
| 669system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use | 669system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use |
| 670system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. | 670system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. |
| 671system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 672system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. | 671system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. 672system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. |
| 673system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 673system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 674system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor 675system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor 676system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy 677system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy 678system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy 679system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id | 674system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor 675system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor 676system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy 677system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy 678system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy 679system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id |
| 680system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id | 680system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id |
| 681system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 682system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id | 681system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id 682system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id |
| 683system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 684system.l2cache.tags.data_accesses 3959 # Number of data accesses | 683system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 684system.l2cache.tags.data_accesses 3959 # Number of data accesses |
| 685system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 685system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 686system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 687system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 688system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 689system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 690system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 691system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 692system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 693system.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 4 unchanged lines hidden (view full) --- 698system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 699system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 700system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 701system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 702system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 703system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 704system.l2cache.overall_misses::cpu.data 126 # number of overall misses 705system.l2cache.overall_misses::total 351 # number of overall misses | 686system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 687system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 688system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 689system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 690system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 691system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 692system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 693system.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 4 unchanged lines hidden (view full) --- 698system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 699system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 700system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 701system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 702system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 703system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 704system.l2cache.overall_misses::cpu.data 126 # number of overall misses 705system.l2cache.overall_misses::total 351 # number of overall misses |
| 706system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles 707system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles 708system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles 709system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles 710system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles 711system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles 712system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles 713system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles 714system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles 715system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles 716system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles | 706system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles 707system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles 708system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles 709system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles 710system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles 711system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles 712system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles 713system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles 714system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles 715system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles 716system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles |
| 717system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 718system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 719system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 720system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 721system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 722system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 723system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 724system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 731system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 732system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 733system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 734system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 735system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 736system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 737system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 738system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses | 717system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 718system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 719system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 720system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 721system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 722system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 723system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 724system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 731system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 732system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 733system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 734system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 735system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 736system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 737system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 738system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses |
| 739system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency 740system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency 741system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency 742system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency 743system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency 744system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 745system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 746system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency 747system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 748system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 749system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency | 739system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency 740system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency 741system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency 742system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency 743system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency 744system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency 745system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency 746system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency 747system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency 748system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency 749system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency |
| 750system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 757system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 758system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 759system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 760system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 761system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 762system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 763system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 764system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 765system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 766system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses | 750system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 757system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 758system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 759system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 760system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 761system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 762system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 763system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 764system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 765system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 766system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses |
| 767system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles 768system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles 769system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles 770system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles 771system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles 772system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles 773system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles 774system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles 775system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles 776system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles 777system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles | 767system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles 768system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles 769system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles 770system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles 771system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles 772system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles 773system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles 774system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles 775system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles 776system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles 777system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles |
| 778system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 779system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 780system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 781system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 782system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 783system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 784system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 785system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 786system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 787system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 788system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses | 778system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 779system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 780system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 781system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 782system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 783system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 784system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 785system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 786system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 787system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 788system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses |
| 789system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency 790system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency 791system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency 792system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 793system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 794system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 795system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 796system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 797system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 798system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 799system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 800system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states | 789system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency 790system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency 791system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency 792system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency 793system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency 794system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency 795system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency 796system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency 797system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency 798system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency 799system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency 800system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. 801system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 802system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 803system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 804system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 805system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 806system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states |
| 801system.membus.trans_dist::ReadResp 308 # Transaction distribution 802system.membus.trans_dist::ReadExReq 43 # Transaction distribution 803system.membus.trans_dist::ReadExResp 43 # Transaction distribution 804system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 805system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 806system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 807system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 808system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 815system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram 816system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 817system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 818system.membus.snoop_fanout::min_value 0 # Request fanout histogram 819system.membus.snoop_fanout::max_value 0 # Request fanout histogram 820system.membus.snoop_fanout::total 351 # Request fanout histogram 821system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) 822system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) | 807system.membus.trans_dist::ReadResp 308 # Transaction distribution 808system.membus.trans_dist::ReadExReq 43 # Transaction distribution 809system.membus.trans_dist::ReadExResp 43 # Transaction distribution 810system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 811system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 812system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 813system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 814system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 821system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram 822system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 823system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 824system.membus.snoop_fanout::min_value 0 # Request fanout histogram 825system.membus.snoop_fanout::max_value 0 # Request fanout histogram 826system.membus.snoop_fanout::total 351 # Request fanout histogram 827system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) 828system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 823system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) | 829system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) |
| 824system.membus.respLayer0.utilization 3.7 # Layer utilization (%) 825 826---------- End Simulation Statistics ---------- | 830system.membus.respLayer0.utilization 3.7 # Layer utilization (%) 831 832---------- End Simulation Statistics ---------- |