| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 372227 # Simulator instruction rate (inst/s) 8host_op_rate 430264 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3715181399 # Simulator tick rate (ticks/s) 10host_mem_usage 693900 # Number of bytes of host memory used | 7host_inst_rate 407452 # Simulator instruction rate (inst/s) 8host_op_rate 470980 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4066768251 # Simulator tick rate (ticks/s) 10host_mem_usage 695596 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states 254system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 253system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 254system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 255system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 273system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 274system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 275system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 276system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 277system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 278system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 279system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 280system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 255system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 260system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 261system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 262system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 276system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 277system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 278system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 279system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 280system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 281system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 282system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 283system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 284system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 281system.cpu.dtb.walker.walks 0 # Table walker walks requested 282system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 283system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 284system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 285system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 302system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 303system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 304system.cpu.dtb.read_accesses 0 # DTB read accesses 305system.cpu.dtb.write_accesses 0 # DTB write accesses 306system.cpu.dtb.inst_accesses 0 # ITB inst accesses 307system.cpu.dtb.hits 0 # DTB hits 308system.cpu.dtb.misses 0 # DTB misses 309system.cpu.dtb.accesses 0 # DTB accesses | 285system.cpu.dtb.walker.walks 0 # Table walker walks requested 286system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 287system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 288system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 289system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 306system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.dtb.read_accesses 0 # DTB read accesses 309system.cpu.dtb.write_accesses 0 # DTB write accesses 310system.cpu.dtb.inst_accesses 0 # ITB inst accesses 311system.cpu.dtb.hits 0 # DTB hits 312system.cpu.dtb.misses 0 # DTB misses 313system.cpu.dtb.accesses 0 # DTB accesses |
| 314system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 310system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 311system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 315system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 336system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 344system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 339system.cpu.itb.walker.walks 0 # Table walker walks requested 340system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 361system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.itb.read_accesses 0 # DTB read accesses 363system.cpu.itb.write_accesses 0 # DTB write accesses 364system.cpu.itb.inst_accesses 0 # ITB inst accesses 365system.cpu.itb.hits 0 # DTB hits 366system.cpu.itb.misses 0 # DTB misses 367system.cpu.itb.accesses 0 # DTB accesses 368system.cpu.workload.num_syscalls 13 # Number of system calls | 345system.cpu.itb.walker.walks 0 # Table walker walks requested 346system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 367system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.itb.read_accesses 0 # DTB read accesses 369system.cpu.itb.write_accesses 0 # DTB write accesses 370system.cpu.itb.inst_accesses 0 # ITB inst accesses 371system.cpu.itb.hits 0 # DTB hits 372system.cpu.itb.misses 0 # DTB misses 373system.cpu.itb.accesses 0 # DTB accesses 374system.cpu.workload.num_syscalls 13 # Number of system calls |
| 375system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states |
|
| 369system.cpu.numCycles 49855 # number of cpu cycles simulated 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 372system.cpu.committedInsts 4988 # Number of instructions committed 373system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 374system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 375system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 376system.cpu.num_func_calls 215 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 421system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 422system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 423system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 424system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 425system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 426system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 427system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 428system.cpu.op_class::total 5831 # Class of executed instruction | 376system.cpu.numCycles 49855 # number of cpu cycles simulated 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 4988 # Number of instructions committed 380system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 381system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 382system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 383system.cpu.num_func_calls 215 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 428system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 429system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 430system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 431system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 432system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 433system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 434system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 435system.cpu.op_class::total 5831 # Class of executed instruction |
| 436system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 429system.cpu.dcache.tags.replacements 0 # number of replacements 430system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use 431system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 432system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 433system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 434system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 435system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor 436system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy 437system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 441system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 442system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 443system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses | 437system.cpu.dcache.tags.replacements 0 # number of replacements 438system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use 439system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 440system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 441system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 442system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 443system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor 444system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 450system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses |
| 452system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 444system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 446system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 447system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 448system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 449system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 450system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 451system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 78 unchanged lines hidden (view full) --- 530system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 531system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 532system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 533system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 534system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 535system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency | 453system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 454system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits 455system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits 456system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits 457system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 458system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 459system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 460system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 78 unchanged lines hidden (view full) --- 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency |
| 547system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 538system.cpu.icache.tags.replacements 70 # number of replacements 539system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use 540system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 541system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 542system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 543system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 544system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 545system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy 546system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy 547system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 548system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 549system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 550system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 551system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 552system.cpu.icache.tags.data_accesses 10305 # Number of data accesses | 548system.cpu.icache.tags.replacements 70 # number of replacements 549system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use 550system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 554system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy 557system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 560system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 561system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 562system.cpu.icache.tags.data_accesses 10305 # Number of data accesses |
| 563system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 553system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 554system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 555system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 556system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 557system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 558system.cpu.icache.overall_hits::total 4779 # number of overall hits 559system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 560system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 619system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 620system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 621system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 622system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 623system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 624system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 564system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 569system.cpu.icache.overall_hits::total 4779 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 630system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 631system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 632system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 633system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 634system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 635system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 636system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 625system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 626system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 627system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 628system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 629system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 630system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 631system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 632system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 646system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 647system.l2bus.snoop_fanout::total 391 # Request fanout histogram 648system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 649system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 650system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 651system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 652system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 653system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) | 637system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 638system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution 639system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 640system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 641system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 642system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) 643system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 644system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 658system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 659system.l2bus.snoop_fanout::total 391 # Request fanout histogram 660system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 661system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 662system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 663system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 664system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 665system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 666system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 654system.l2cache.tags.replacements 0 # number of replacements 655system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use 656system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 657system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 658system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. 659system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor 661system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor 662system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy 663system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy 664system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy 665system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 666system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 667system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 668system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id 669system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 670system.l2cache.tags.data_accesses 3959 # Number of data accesses | 667system.l2cache.tags.replacements 0 # number of replacements 668system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use 669system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 670system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 671system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. 672system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 673system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor 674system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor 675system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy 676system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy 677system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy 678system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 679system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 680system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 681system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id 682system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 683system.l2cache.tags.data_accesses 3959 # Number of data accesses |
| 684system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 671system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 672system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 673system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 674system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 675system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 676system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 677system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 678system.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 98 unchanged lines hidden (view full) --- 777system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 778system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 779system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 780system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 781system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 782system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 783system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 784system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency | 685system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 686system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 687system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits 688system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 689system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 690system.l2cache.demand_hits::total 40 # number of demand (read+write) hits 691system.l2cache.overall_hits::cpu.inst 24 # number of overall hits 692system.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 98 unchanged lines hidden (view full) --- 791system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 792system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 793system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 794system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 795system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 796system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 797system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 798system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency |
| 799system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states |
|
| 785system.membus.trans_dist::ReadResp 308 # Transaction distribution 786system.membus.trans_dist::ReadExReq 43 # Transaction distribution 787system.membus.trans_dist::ReadExResp 43 # Transaction distribution 788system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 789system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 790system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 791system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 792system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 800system.membus.trans_dist::ReadResp 308 # Transaction distribution 801system.membus.trans_dist::ReadExReq 43 # Transaction distribution 802system.membus.trans_dist::ReadExResp 43 # Transaction distribution 803system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 804system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 805system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 806system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 807system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |