| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 411650 # Simulator instruction rate (inst/s) 8host_op_rate 475781 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4107877451 # Simulator tick rate (ticks/s) 10host_mem_usage 655016 # Number of bytes of host memory used | 7host_inst_rate 523400 # Simulator instruction rate (inst/s) 8host_op_rate 604831 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5220928914 # Simulator tick rate (ticks/s) 10host_mem_usage 655332 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory --- 479 unchanged lines hidden (view full) --- 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory --- 479 unchanged lines hidden (view full) --- 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 506system.cpu.dcache.fast_writes 0 # number of fast writes performed 507system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 508system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 509system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 510system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 511system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 512system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 513system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 514system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 515system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 537system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 539system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency | 506system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 507system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 508system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 509system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 510system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 511system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 512system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 513system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 530system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 531system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 532system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 533system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 534system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 535system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency |
| 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 541system.cpu.icache.tags.replacements 70 # number of replacements 542system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use 543system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 544system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 545system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 547system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 548system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 590system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 591system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency 592system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 538system.cpu.icache.tags.replacements 70 # number of replacements 539system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use 540system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 541system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 542system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 543system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 544system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 545system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 587system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 588system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency 589system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 590system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 591system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 592system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 594system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 598system.cpu.icache.fast_writes 0 # number of fast writes performed 599system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 600system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 601system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 602system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 603system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 604system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 605system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses 606system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 616system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 617system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency | 595system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 596system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 597system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 598system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 599system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 600system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses 601system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 611system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 612system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency 614system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 616system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency |
| 624system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 625system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 626system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 627system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 628system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 629system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 630system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 631system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 632system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution --- 106 unchanged lines hidden (view full) --- 739system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 740system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency 741system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 619system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 620system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 621system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 622system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 623system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 624system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 625system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 626system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution --- 106 unchanged lines hidden (view full) --- 733system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 734system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency 735system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 739system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 747system.l2cache.fast_writes 0 # number of fast writes performed 748system.l2cache.cache_copies 0 # number of cache copies performed | |
| 749system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 750system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 751system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 752system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 753system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 754system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 755system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 756system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 785system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 786system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 787system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 788system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 789system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 790system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 791system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 792system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency | 741system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 742system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 743system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 744system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 745system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 746system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 747system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 748system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 777system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 778system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 779system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 780system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 781system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 782system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 783system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 784system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency |
| 793system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 794system.membus.trans_dist::ReadResp 308 # Transaction distribution 795system.membus.trans_dist::ReadExReq 43 # Transaction distribution 796system.membus.trans_dist::ReadExResp 43 # Transaction distribution 797system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 798system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 799system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 800system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 801system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 785system.membus.trans_dist::ReadResp 308 # Transaction distribution 786system.membus.trans_dist::ReadExReq 43 # Transaction distribution 787system.membus.trans_dist::ReadExResp 43 # Transaction distribution 788system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 789system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 790system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 791system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) 792system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |