| stats.txt (11106:878dd30741c4) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000050 # Number of seconds simulated 4sim_ticks 49855000 # Number of ticks simulated 5final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79800 # Simulator instruction rate (inst/s) 8host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 797317444 # Simulator tick rate (ticks/s) 10host_mem_usage 690160 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 351391 # Simulator instruction rate (inst/s) 8host_op_rate 406109 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3506224066 # Simulator tick rate (ticks/s) 10host_mem_usage 699088 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory --- 174 unchanged lines hidden (view full) --- 194system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation | 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory --- 174 unchanged lines hidden (view full) --- 194system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation |
| 202system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing 203system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM | 202system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing 203system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers | 204system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers |
| 205system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst | 205system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst |
| 206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst | 207system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst |
| 208system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s 209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage 214system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads 215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 222system.mem_ctrl.avgGap 141757.83 # Average gap between requests 223system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined 224system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) 225system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 226system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) 227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 208system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s 209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage 214system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads 215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 222system.mem_ctrl.avgGap 141757.83 # Average gap between requests 223system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined 224system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) 225system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 226system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) 227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 229system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) | 229system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) |
| 230system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) | 230system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) |
| 231system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) 232system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) 233system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states | 231system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) 232system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) 233system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states |
| 234system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 234system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 236system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states | 236system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states |
| 237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) 239system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) 240system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) 241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) | 237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) 239system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) 240system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) 241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) |
| 243system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) 244system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states | 243system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) 244system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states |
| 248system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 248system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 250system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states | 250system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states |
| 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 253system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 254system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 255system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 163 unchanged lines hidden (view full) --- 422system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 423system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 424system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 425system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 426system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 427system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 428system.cpu.op_class::total 5831 # Class of executed instruction 429system.cpu.dcache.tags.replacements 0 # number of replacements | 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 253system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 254system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 255system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 256system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 257system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 258system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 163 unchanged lines hidden (view full) --- 422system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 423system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 424system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 425system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 426system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 427system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 428system.cpu.op_class::total 5831 # Class of executed instruction 429system.cpu.dcache.tags.replacements 0 # number of replacements |
| 430system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use | 430system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use |
| 431system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 432system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 433system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 434system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 431system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. 432system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 433system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. 434system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 435system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor 436system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy 437system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy | 435system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor 436system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy 437system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy |
| 438system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 441system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 442system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 443system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses 444system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 456system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 460system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 463system.cpu.dcache.overall_misses::total 142 # number of overall misses | 438system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 441system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id 442system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses 443system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses 444system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 456system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 460system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses 463system.cpu.dcache.overall_misses::total 142 # number of overall misses |
| 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles 468system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles 469system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles 470system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles 471system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles | 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles 468system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles 469system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles 470system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles 471system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles |
| 472system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 473system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 475system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 477system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 484system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 485system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 486system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 487system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 488system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 489system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 490system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 491system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses | 472system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) 473system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 475system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 477system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 484system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses 485system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses 486system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses 487system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses 488system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses 489system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses 490system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses 491system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses |
| 492system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency 493system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency 495system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency 496system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency 497system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency | 492system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency 493system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency 495system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency 496system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 497system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency |
| 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu.dcache.fast_writes 0 # number of fast writes performed 507system.cpu.dcache.cache_copies 0 # number of cache copies performed 508system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 509system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 510system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 511system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 512system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 513system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 514system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 515system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 500system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu.dcache.fast_writes 0 # number of fast writes performed 507system.cpu.dcache.cache_copies 0 # number of cache copies performed 508system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 509system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 510system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 511system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 512system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 513system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 514system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 515system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 516system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles 517system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles 518system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles 519system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles 520system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles 521system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles 522system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles 523system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles | 516system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles 517system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles 518system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles 519system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles 520system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles 521system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles 522system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles 523system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles |
| 524system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 525system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 526system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 527system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 528system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 529system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 530system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 531system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses | 524system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses 525system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses 526system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses 527system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses 528system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses 529system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses 530system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses 531system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses |
| 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency 533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency 535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency 537system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency 539system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency | 532system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency 533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency 534system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency 535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency 536system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 537system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency 538system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency 539system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency |
| 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 541system.cpu.icache.tags.replacements 70 # number of replacements | 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 541system.cpu.icache.tags.replacements 70 # number of replacements |
| 542system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use | 542system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use |
| 543system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 544system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 545system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 543system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. 544system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. 545system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. 546system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 547system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor 548system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy 549system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy | 547system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor 548system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy 549system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy |
| 550system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 551system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 552system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 553system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 554system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 555system.cpu.icache.tags.data_accesses 10305 # Number of data accesses 556system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 557system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 558system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 559system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 560system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 561system.cpu.icache.overall_hits::total 4779 # number of overall hits 562system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 563system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 564system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 565system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 566system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 567system.cpu.icache.overall_misses::total 249 # number of overall misses | 550system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id 551system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 552system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 553system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id 554system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses 555system.cpu.icache.tags.data_accesses 10305 # Number of data accesses 556system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits 557system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits 558system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits 559system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits 560system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits 561system.cpu.icache.overall_hits::total 4779 # number of overall hits 562system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses 563system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses 564system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses 565system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses 566system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses 567system.cpu.icache.overall_misses::total 249 # number of overall misses |
| 568system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles 569system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles 570system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles 571system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles 572system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles 573system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles | 568system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles 569system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles 570system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles 571system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles 572system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles 573system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles |
| 574system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 575system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 576system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 577system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 578system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 579system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 580system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 581system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 582system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 583system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 584system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 585system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses | 574system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) 575system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) 576system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses 577system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses 578system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses 579system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses 580system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses 581system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses 582system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses 583system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses 584system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses 585system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses |
| 586system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency 587system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency 588system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency 589system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency 590system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency 591system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency | 586system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency 587system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency 588system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 589system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency 590system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency 591system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency |
| 592system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 598system.cpu.icache.fast_writes 0 # number of fast writes performed 599system.cpu.icache.cache_copies 0 # number of cache copies performed 600system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 601system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 602system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 603system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 604system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 605system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses | 592system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 598system.cpu.icache.fast_writes 0 # number of fast writes performed 599system.cpu.icache.cache_copies 0 # number of cache copies performed 600system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses 601system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 602system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses 603system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 604system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses 605system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses |
| 606system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles 608system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles 609system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles 610system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles 611system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles | 606system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles 608system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles 609system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles 610system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles 611system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles |
| 612system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 613system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 614system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 615system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 616system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 617system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses | 612system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses 613system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses 614system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses 615system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses 616system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses 617system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses |
| 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency | 618system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency 619system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency 620system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 621system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency 622system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency 623system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency |
| 624system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 624system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 625system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. 626system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. 627system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 628system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 629system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 630system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 625system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 626system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution 627system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 628system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 629system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 630system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 631system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 632system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 633system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) 634system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 635system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 636system.l2bus.snoops 0 # Total snoops (count) 637system.l2bus.snoop_fanout::samples 461 # Request fanout histogram | 631system.l2bus.trans_dist::ReadResp 348 # Transaction distribution 632system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution 633system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution 634system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution 635system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution 636system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 637system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 638system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 639system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) 640system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 641system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 642system.l2bus.snoops 0 # Total snoops (count) 643system.l2bus.snoop_fanout::samples 461 # Request fanout histogram |
| 638system.l2bus.snoop_fanout::mean 1 # Request fanout histogram 639system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram | 644system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram 645system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram |
| 640system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 646system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 641system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 642system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram | 647system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram 648system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram |
| 643system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 644system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 649system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 650system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 645system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram | 651system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 646system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 647system.l2bus.snoop_fanout::total 461 # Request fanout histogram 648system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 649system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 650system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 651system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 652system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 653system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) 654system.l2cache.tags.replacements 0 # number of replacements | 652system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 653system.l2bus.snoop_fanout::total 461 # Request fanout histogram 654system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) 655system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) 656system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) 657system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) 658system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) 659system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) 660system.l2cache.tags.replacements 0 # number of replacements |
| 655system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use | 661system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use |
| 656system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 657system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 658system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. 659system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 662system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. 663system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 664system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. 665system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 660system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor 661system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor 662system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy 663system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy 664system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy | 666system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor 667system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor 668system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy 669system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy 670system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy |
| 665system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 666system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 667system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 668system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id 669system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 670system.l2cache.tags.data_accesses 3959 # Number of data accesses 671system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 672system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits --- 10 unchanged lines hidden (view full) --- 683system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 684system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 685system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 686system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 687system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 688system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 689system.l2cache.overall_misses::cpu.data 126 # number of overall misses 690system.l2cache.overall_misses::total 351 # number of overall misses | 671system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 672system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 673system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 674system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id 675system.l2cache.tags.tag_accesses 3959 # Number of tag accesses 676system.l2cache.tags.data_accesses 3959 # Number of data accesses 677system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits 678system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits --- 10 unchanged lines hidden (view full) --- 689system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 690system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses 691system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 692system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 693system.l2cache.demand_misses::total 351 # number of demand (read+write) misses 694system.l2cache.overall_misses::cpu.inst 225 # number of overall misses 695system.l2cache.overall_misses::cpu.data 126 # number of overall misses 696system.l2cache.overall_misses::total 351 # number of overall misses |
| 691system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles 692system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles 693system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles 694system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles 695system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles 696system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles 697system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles 698system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles 699system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles 700system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles 701system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles | 697system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles 698system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles 699system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles 700system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles 701system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles 702system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles 703system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles 704system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles 705system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles 706system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles 707system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles |
| 702system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 703system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 704system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 705system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 706system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 707system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 708system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 709system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 716system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 717system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 718system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 719system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 720system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 721system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 722system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 723system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses | 708system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 709system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 710system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) 711system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 712system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) 713system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses 714system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 715system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 722system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses 723system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses 724system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses 725system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses 726system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses 727system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses 728system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses 729system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses |
| 724system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency 725system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency 726system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency 727system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency 728system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency 729system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency 730system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency 731system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency 732system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency 733system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency 734system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency | 730system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency 731system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency 732system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency 733system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency 734system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency 735system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 736system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 737system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency 738system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency 739system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency 740system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency |
| 735system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 739system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.l2cache.fast_writes 0 # number of fast writes performed 742system.l2cache.cache_copies 0 # number of cache copies performed 743system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 744system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 745system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 746system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 747system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 748system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 749system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 750system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 751system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 752system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 753system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses | 741system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.l2cache.fast_writes 0 # number of fast writes performed 748system.l2cache.cache_copies 0 # number of cache copies performed 749system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 750system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 751system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses 752system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses 753system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses 754system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 755system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 756system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 757system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 758system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses 759system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses |
| 754system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles 755system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles 756system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles 757system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles 758system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles 759system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles 760system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles 761system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles 762system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles 763system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles 764system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles | 760system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles 761system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles 762system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles 763system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles 764system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles 765system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles 766system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles 767system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles 768system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles 769system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles 770system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles |
| 765system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 766system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 767system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 768system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 769system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 770system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 771system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 772system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 773system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 774system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 775system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses | 771system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 772system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 773system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses 774system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses 775system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses 776system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses 777system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses 778system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses 779system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses 780system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses 781system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses |
| 776system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency 777system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency 778system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency 779system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency 780system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency 781system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency 782system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency 783system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency 784system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency 785system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency 786system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency | 782system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency 783system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency 784system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency 785system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency 786system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency 787system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 788system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 789system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency 790system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency 791system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency 792system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency |
| 787system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 788system.membus.trans_dist::ReadResp 308 # Transaction distribution 789system.membus.trans_dist::ReadExReq 43 # Transaction distribution 790system.membus.trans_dist::ReadExResp 43 # Transaction distribution 791system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 792system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 793system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 794system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- | 793system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.membus.trans_dist::ReadResp 308 # Transaction distribution 795system.membus.trans_dist::ReadExReq 43 # Transaction distribution 796system.membus.trans_dist::ReadExResp 43 # Transaction distribution 797system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution 798system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) 799system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) 800system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- |