3,5c3,5
< sim_seconds 0.000050 # Number of seconds simulated
< sim_ticks 50074000 # Number of ticks simulated
< final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000052 # Number of seconds simulated
> sim_ticks 52453000 # Number of ticks simulated
> final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 207988 # Simulator instruction rate (inst/s)
< host_op_rate 240459 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2085706484 # Simulator tick rate (ticks/s)
< host_mem_usage 655032 # Number of bytes of host memory used
---
> host_inst_rate 234245 # Simulator instruction rate (inst/s)
> host_op_rate 270642 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2457731659 # Simulator tick rate (ticks/s)
> host_mem_usage 654144 # Number of bytes of host memory used
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 49975000 # Total gap between requests
---
> system.mem_ctrl.totGap 52348000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads
223,225c223,225
< system.mem_ctrl.avgGap 142378.92 # Average gap between requests
< system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ)
---
> system.mem_ctrl.avgGap 149139.60 # Average gap between requests
> system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ)
227c227
< system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ)
229,234c229,238
< system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states
---
> system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states
236,241c240,246
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states
> system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ)
243,248c248,257
< system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states
---
> system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states
250,254c259,264
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
284c294
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
314c324
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
344c354
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
375,376c385,386
< system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 50074 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 52453 # number of cpu cycles simulated
397c407
< system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles
436c446
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
438c448
< system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use
443,445c453,455
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy
452c462
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
473,480c483,490
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles
501,508c511,518
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency
523,530c533,540
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles
539,547c549,557
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
549c559
< system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use
554,556c564,566
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy
558,559c568,569
< system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
563c573
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
576,581c586,591
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles
594,599c604,609
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency
612,617c622,627
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles
624,629c634,639
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency
636c646
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
664c674
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
666,667c676,677
< system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%)
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
669c679
< system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use
674,678c684,688
< system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy
680,681c690,691
< system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id
685c695
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
706,716c716,726
< system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles
739,749c749,759
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency
767,777c777,787
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles
789,799c799,809
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency
806c816
< system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
829,830c839,840
< system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.6 # Layer utilization (%)
< sim_seconds 0.000050 # Number of seconds simulated
< sim_ticks 50074000 # Number of ticks simulated
< final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000052 # Number of seconds simulated
> sim_ticks 52453000 # Number of ticks simulated
> final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 207988 # Simulator instruction rate (inst/s)
< host_op_rate 240459 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2085706484 # Simulator tick rate (ticks/s)
< host_mem_usage 655032 # Number of bytes of host memory used
---
> host_inst_rate 234245 # Simulator instruction rate (inst/s)
> host_op_rate 270642 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2457731659 # Simulator tick rate (ticks/s)
> host_mem_usage 654144 # Number of bytes of host memory used
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 49975000 # Total gap between requests
---
> system.mem_ctrl.totGap 52348000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads
223,225c223,225
< system.mem_ctrl.avgGap 142378.92 # Average gap between requests
< system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ)
---
> system.mem_ctrl.avgGap 149139.60 # Average gap between requests
> system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ)
227c227
< system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ)
229,234c229,238
< system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states
---
> system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states
236,241c240,246
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states
> system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ)
243,248c248,257
< system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states
---
> system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states
250,254c259,264
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
284c294
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
314c324
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
344c354
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
375,376c385,386
< system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 50074 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 52453 # number of cpu cycles simulated
397c407
< system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles
436c446
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
438c448
< system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use
443,445c453,455
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy
452c462
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
473,480c483,490
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles
501,508c511,518
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency
523,530c533,540
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles
539,547c549,557
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
549c559
< system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use
554,556c564,566
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy
558,559c568,569
< system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
563c573
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
576,581c586,591
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles
594,599c604,609
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency
612,617c622,627
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles
624,629c634,639
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency
636c646
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
664c674
< system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
666,667c676,677
< system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%)
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
669c679
< system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use
674,678c684,688
< system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy
680,681c690,691
< system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id
685c695
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
706,716c716,726
< system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles
739,749c749,759
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency
767,777c777,787
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles
789,799c799,809
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency
806c816
< system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states
829,830c839,840
< system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.6 # Layer utilization (%)