4,5c4,5
< sim_ticks 49855000 # Number of ticks simulated
< final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 50074000 # Number of ticks simulated
> final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 256506 # Simulator instruction rate (inst/s)
< host_op_rate 296356 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2557788683 # Simulator tick rate (ticks/s)
< host_mem_usage 651420 # Number of bytes of host memory used
---
> host_inst_rate 207988 # Simulator instruction rate (inst/s)
> host_op_rate 240459 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2085706484 # Simulator tick rate (ticks/s)
> host_mem_usage 655032 # Number of bytes of host memory used
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 49757000 # Total gap between requests
---
> system.mem_ctrl.totGap 49975000 # Total gap between requests
192,193c192,193
< system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation
---
> system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation
196,197c196,197
< system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation
---
> system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation
203,204c203,204
< system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads
223c223
< system.mem_ctrl.avgGap 141757.83 # Average gap between requests
---
> system.mem_ctrl.avgGap 142378.92 # Average gap between requests
227c227
< system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ)
230,234c230,234
< system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states
237c237
< system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states
244,248c244,248
< system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states
251c251
< system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states
253,254c253,254
< system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
284c284
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
314c314
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
344c344
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
375,376c375,376
< system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 49855 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 50074 # number of cpu cycles simulated
397c397
< system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles
436c436
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
438c438
< system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use
443,445c443,445
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy
452c452
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
473,480c473,480
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles
501,508c501,508
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency
523,530c523,530
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles
539,547c539,547
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
549c549
< system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use
554,556c554,556
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy
558,559c558,559
< system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
563c563
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
576,581c576,581
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles
594,599c594,599
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency
612,617c612,617
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles
624,629c624,629
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
636c636
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
667c667
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
669c669
< system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use
671,672c671,672
< system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks.
674,679c674,679
< system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
681,682c681,682
< system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id
685c685
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
706,716c706,716
< system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles
739,749c739,749
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency
767,777c767,777
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles
789,800c789,806
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
823c829
< system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks)
< sim_ticks 49855000 # Number of ticks simulated
< final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 50074000 # Number of ticks simulated
> final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 256506 # Simulator instruction rate (inst/s)
< host_op_rate 296356 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2557788683 # Simulator tick rate (ticks/s)
< host_mem_usage 651420 # Number of bytes of host memory used
---
> host_inst_rate 207988 # Simulator instruction rate (inst/s)
> host_op_rate 240459 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2085706484 # Simulator tick rate (ticks/s)
> host_mem_usage 655032 # Number of bytes of host memory used
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 49757000 # Total gap between requests
---
> system.mem_ctrl.totGap 49975000 # Total gap between requests
192,193c192,193
< system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation
---
> system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation
196,197c196,197
< system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation
---
> system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation
203,204c203,204
< system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads
223c223
< system.mem_ctrl.avgGap 141757.83 # Average gap between requests
---
> system.mem_ctrl.avgGap 142378.92 # Average gap between requests
227c227
< system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ)
230,234c230,234
< system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states
---
> system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states
237c237
< system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states
244,248c244,248
< system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states
251c251
< system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states
253,254c253,254
< system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
284c284
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
314c314
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
344c344
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
375,376c375,376
< system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 49855 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 50074 # number of cpu cycles simulated
397c397
< system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles
436c436
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
438c438
< system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use
443,445c443,445
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy
452c452
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
473,480c473,480
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles
501,508c501,508
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency
523,530c523,530
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles
539,547c539,547
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
549c549
< system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use
554,556c554,556
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy
558,559c558,559
< system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
563c563
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
576,581c576,581
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles
594,599c594,599
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency
612,617c612,617
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles
624,629c624,629
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency
636c636
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
667c667
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
669c669
< system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use
671,672c671,672
< system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
< system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks.
---
> system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks.
> system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks.
674,679c674,679
< system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy
< system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy
> system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
681,682c681,682
< system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
< system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id
---
> system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
> system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id
685c685
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
706,716c706,716
< system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles
739,749c739,749
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency
767,777c767,777
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles
789,800c789,806
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states
823c829
< system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks)