7,11c7,11
< host_inst_rate 79800 # Simulator instruction rate (inst/s)
< host_op_rate 92294 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 797317444 # Simulator tick rate (ticks/s)
< host_mem_usage 690160 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 351391 # Simulator instruction rate (inst/s)
> host_op_rate 406109 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3506224066 # Simulator tick rate (ticks/s)
> host_mem_usage 699088 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
202,203c202,203
< system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst
207c207
< system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst
---
> system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst
229c229
< system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ)
---
> system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ)
231,233c231,233
< system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states
---
> system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states
236c236
< system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states
243,247c243,247
< system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states
250c250
< system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
430c430
< system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
435,437c435,437
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy
464,471c464,471
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles
492,499c492,499
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency
516,523c516,523
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles
532,539c532,539
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
542c542
< system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
547,549c547,549
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy
568,573c568,573
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles
586,591c586,591
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency
606,611c606,611
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles
618,623c618,623
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
624a625,630
> system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
638,639c644,645
< system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
< system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram
> system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram
641,642c647,648
< system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram
---
> system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram
> system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram
645c651
< system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
655c661
< system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
660,664c666,670
< system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy
691,701c697,707
< system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles
724,734c730,740
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency
754,764c760,770
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles
776,786c782,792
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
< host_inst_rate 79800 # Simulator instruction rate (inst/s)
< host_op_rate 92294 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 797317444 # Simulator tick rate (ticks/s)
< host_mem_usage 690160 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 351391 # Simulator instruction rate (inst/s)
> host_op_rate 406109 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3506224066 # Simulator tick rate (ticks/s)
> host_mem_usage 699088 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
202,203c202,203
< system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst
207c207
< system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst
---
> system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst
229c229
< system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ)
---
> system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ)
231,233c231,233
< system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states
---
> system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW)
> system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states
236c236
< system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states
---
> system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states
243,247c243,247
< system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states
---
> system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW)
> system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states
250c250
< system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states
---
> system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
430c430
< system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
435,437c435,437
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy
464,471c464,471
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles
492,499c492,499
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency
516,523c516,523
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles
532,539c532,539
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
542c542
< system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
547,549c547,549
< system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy
568,573c568,573
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles
586,591c586,591
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency
606,611c606,611
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles
618,623c618,623
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
624a625,630
> system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
638,639c644,645
< system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
< system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram
> system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram
641,642c647,648
< system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram
---
> system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram
> system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram
645c651
< system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
655c661
< system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
660,664c666,670
< system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy
691,701c697,707
< system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles
724,734c730,740
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency
754,764c760,770
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles
776,786c782,792
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency