1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000052 # Number of seconds simulated 4sim_ticks 52453000 # Number of ticks simulated 5final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 494492 # Simulator instruction rate (inst/s) 8host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5188174566 # Simulator tick rate (ticks/s) 10host_mem_usage 654324 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 351 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 52348000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 149139.60 # Average gap between requests 224system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states 244system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 264system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 265system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 274system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 275system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 276system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 277system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 278system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 289system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 290system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 291system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 292system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 293system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 294system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 295system.cpu.dtb.walker.walks 0 # Table walker walks requested 296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 355system.cpu.itb.walker.walks 0 # Table walker walks requested 356system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.inst_hits 0 # ITB inst hits 364system.cpu.itb.inst_misses 0 # ITB inst misses 365system.cpu.itb.read_hits 0 # DTB read hits 366system.cpu.itb.read_misses 0 # DTB read misses 367system.cpu.itb.write_hits 0 # DTB write hits 368system.cpu.itb.write_misses 0 # DTB write misses 369system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.itb.read_accesses 0 # DTB read accesses 379system.cpu.itb.write_accesses 0 # DTB write accesses 380system.cpu.itb.inst_accesses 0 # ITB inst accesses 381system.cpu.itb.hits 0 # DTB hits 382system.cpu.itb.misses 0 # DTB misses 383system.cpu.itb.accesses 0 # DTB accesses
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000052 # Number of seconds simulated 4sim_ticks 52453000 # Number of ticks simulated 5final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 494492 # Simulator instruction rate (inst/s) 8host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5188174566 # Simulator tick rate (ticks/s) 10host_mem_usage 654324 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 351 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 52348000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 149139.60 # Average gap between requests 224system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states 244system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 264system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 265system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 274system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 275system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 276system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 277system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 278system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 289system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 290system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 291system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 292system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 293system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 294system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 295system.cpu.dtb.walker.walks 0 # Table walker walks requested 296system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.inst_hits 0 # ITB inst hits 304system.cpu.dtb.inst_misses 0 # ITB inst misses 305system.cpu.dtb.read_hits 0 # DTB read hits 306system.cpu.dtb.read_misses 0 # DTB read misses 307system.cpu.dtb.write_hits 0 # DTB write hits 308system.cpu.dtb.write_misses 0 # DTB write misses 309system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 310system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 313system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 314system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 315system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dtb.read_accesses 0 # DTB read accesses 319system.cpu.dtb.write_accesses 0 # DTB write accesses 320system.cpu.dtb.inst_accesses 0 # ITB inst accesses 321system.cpu.dtb.hits 0 # DTB hits 322system.cpu.dtb.misses 0 # DTB misses 323system.cpu.dtb.accesses 0 # DTB accesses 324system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states 355system.cpu.itb.walker.walks 0 # Table walker walks requested 356system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.inst_hits 0 # ITB inst hits 364system.cpu.itb.inst_misses 0 # ITB inst misses 365system.cpu.itb.read_hits 0 # DTB read hits 366system.cpu.itb.read_misses 0 # DTB read misses 367system.cpu.itb.write_hits 0 # DTB write hits 368system.cpu.itb.write_misses 0 # DTB write misses 369system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.itb.read_accesses 0 # DTB read accesses 379system.cpu.itb.write_accesses 0 # DTB write accesses 380system.cpu.itb.inst_accesses 0 # ITB inst accesses 381system.cpu.itb.hits 0 # DTB hits 382system.cpu.itb.misses 0 # DTB misses 383system.cpu.itb.accesses 0 # DTB accesses
|