| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000333 # Number of seconds simulated 4sim_ticks 332645000 # Number of ticks simulated 5final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000372 # Number of seconds simulated 4sim_ticks 372284000 # Number of ticks simulated 5final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 141116 # Simulator instruction rate (inst/s) 8host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9403646091 # Simulator tick rate (ticks/s) 10host_mem_usage 651444 # Number of bytes of host memory used | 7host_inst_rate 131983 # Simulator instruction rate (inst/s) 8host_op_rate 152589 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9840410910 # Simulator tick rate (ticks/s) 10host_mem_usage 650048 # Number of bytes of host memory used |
| 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory 22system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory 23system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory 24system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory 25system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory 26system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory 27system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory 28system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory 22system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory 23system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory 24system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory 25system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory 26system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory 27system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory 28system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory |
| 29system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) 31system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) 32system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) 33system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) 34system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) 35system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) 36system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) 37system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) 38system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) | 29system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) 31system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) 32system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) 33system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) 34system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) 35system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) 36system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) 37system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) 38system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) |
| 39system.mem_ctrl.readReqs 6089 # Number of read requests accepted 40system.mem_ctrl.writeReqs 936 # Number of write requests accepted 41system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue 42system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue 43system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM 44system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue 45system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM 46system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 77system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts 78system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts 79system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts 80system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 81system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 82system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 83system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 84system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 39system.mem_ctrl.readReqs 6089 # Number of read requests accepted 40system.mem_ctrl.writeReqs 936 # Number of write requests accepted 41system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue 42system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue 43system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM 44system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue 45system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM 46system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 77system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts 78system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts 79system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts 80system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 81system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 82system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 83system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 84system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.mem_ctrl.totGap 332568000 # Total gap between requests | 85system.mem_ctrl.totGap 372207000 # Total gap between requests |
| 86system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) 87system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) 88system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) 89system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) 90system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 91system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 92system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) 93system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 188system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see | 86system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) 87system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) 88system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) 89system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) 90system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 91system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 92system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) 93system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 188system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation 207system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation 208system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation 209system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation | 196system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation 203system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation 204system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation 205system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation 206system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation 207system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation 208system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation 209system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation |
| 210system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes 211system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes 212system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes 213system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes 214system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes 215system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes 216system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes 217system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes 218system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes 219system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads 220system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads 221system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads 222system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads 223system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads | 210system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes 211system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes 212system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes 213system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes 214system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes 215system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes 216system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes 217system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes 218system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes 219system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads 220system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads 221system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads 222system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads 223system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads |
| 224system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing 225system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM | 224system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing 225system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM |
| 226system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers | 226system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers |
| 227system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst | 227system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst |
| 228system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 228system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 229system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst 230system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s 231system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s 232system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s 233system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s | 229system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst 230system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s 231system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s 232system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s 233system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s |
| 234system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 234system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 235system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage 236system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads 237system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes | 235system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage 236system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads 237system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes |
| 238system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 239system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing | 238system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 239system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing |
| 240system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads | 240system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads |
| 241system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes | 241system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes |
| 242system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads | 242system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads |
| 243system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes | 243system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes |
| 244system.mem_ctrl.avgGap 47340.64 # Average gap between requests 245system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined 246system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) 247system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) 248system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) | 244system.mem_ctrl.avgGap 52983.20 # Average gap between requests 245system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined 246system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) 247system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) 248system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) |
| 249system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 249system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 250system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) 251system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) 252system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) 253system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) 254system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) 255system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states 256system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states 257system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 258system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states 259system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 260system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) 261system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) 262system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) 263system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) 264system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) 265system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) 266system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) 267system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) 268system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) 269system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states 270system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states 271system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 272system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states 273system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 274system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states 275system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 250system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) 251system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) 252system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) 253system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) 254system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) 255system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 256system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) 257system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) 258system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank 259system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states 260system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states 261system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 262system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states 263system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states 264system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states 265system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) 266system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) 267system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) 268system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) 269system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) 270system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) 271system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) 272system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) 273system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) 274system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) 275system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) 276system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) 277system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank 278system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states 279system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states 280system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states 281system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states 282system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states 283system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states 284system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states 285system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 276system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 297system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 298system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 299system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 300system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 301system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 302system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 303system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 304system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 286system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 307system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 308system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 309system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 310system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 311system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 312system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 313system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 314system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 305system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 315system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 306system.cpu.dtb.walker.walks 0 # Table walker walks requested 307system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 327system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.dtb.read_accesses 0 # DTB read accesses 330system.cpu.dtb.write_accesses 0 # DTB write accesses 331system.cpu.dtb.inst_accesses 0 # ITB inst accesses 332system.cpu.dtb.hits 0 # DTB hits 333system.cpu.dtb.misses 0 # DTB misses 334system.cpu.dtb.accesses 0 # DTB accesses | 316system.cpu.dtb.walker.walks 0 # Table walker walks requested 317system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 337system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 338system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 339system.cpu.dtb.read_accesses 0 # DTB read accesses 340system.cpu.dtb.write_accesses 0 # DTB write accesses 341system.cpu.dtb.inst_accesses 0 # ITB inst accesses 342system.cpu.dtb.hits 0 # DTB hits 343system.cpu.dtb.misses 0 # DTB misses 344system.cpu.dtb.accesses 0 # DTB accesses |
| 335system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 345system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 336system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 357system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 360system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 361system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 362system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 363system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 364system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 346system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 367system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 365system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 375system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 366system.cpu.itb.walker.walks 0 # Table walker walks requested 367system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 388system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.itb.read_accesses 0 # DTB read accesses 390system.cpu.itb.write_accesses 0 # DTB write accesses 391system.cpu.itb.inst_accesses 0 # ITB inst accesses 392system.cpu.itb.hits 0 # DTB hits 393system.cpu.itb.misses 0 # DTB misses 394system.cpu.itb.accesses 0 # DTB accesses 395system.cpu.workload.num_syscalls 13 # Number of system calls | 376system.cpu.itb.walker.walks 0 # Table walker walks requested 377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.itb.read_accesses 0 # DTB read accesses 400system.cpu.itb.write_accesses 0 # DTB write accesses 401system.cpu.itb.inst_accesses 0 # ITB inst accesses 402system.cpu.itb.hits 0 # DTB hits 403system.cpu.itb.misses 0 # DTB misses 404system.cpu.itb.accesses 0 # DTB accesses 405system.cpu.workload.num_syscalls 13 # Number of system calls |
| 396system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states 397system.cpu.numCycles 332645 # number of cpu cycles simulated | 406system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states 407system.cpu.numCycles 372284 # number of cpu cycles simulated |
| 398system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 399system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 400system.cpu.committedInsts 4988 # Number of instructions committed 401system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 402system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 403system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 404system.cpu.num_func_calls 215 # number of times a function call or return occured 405system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 410system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 411system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 412system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 413system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 414system.cpu.num_mem_refs 2035 # number of memory refs 415system.cpu.num_load_insts 1085 # Number of load instructions 416system.cpu.num_store_insts 950 # Number of store instructions 417system.cpu.num_idle_cycles 0.001000 # Number of idle cycles | 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.committedInsts 4988 # Number of instructions committed 411system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 412system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 413system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 414system.cpu.num_func_calls 215 # number of times a function call or return occured 415system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 420system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 421system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 422system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read 423system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written 424system.cpu.num_mem_refs 2035 # number of memory refs 425system.cpu.num_load_insts 1085 # Number of load instructions 426system.cpu.num_store_insts 950 # Number of store instructions 427system.cpu.num_idle_cycles 0.001000 # Number of idle cycles |
| 418system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles | 428system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles |
| 419system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 420system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 421system.cpu.Branches 1107 # Number of branches fetched 422system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 423system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 424system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 425system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 426system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction --- 28 unchanged lines hidden (view full) --- 455system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 456system.cpu.op_class::total 5831 # Class of executed instruction 457system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 458system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 459system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 460system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 461system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 462system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 429system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 430system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 431system.cpu.Branches 1107 # Number of branches fetched 432system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 433system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction 434system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction 435system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction 436system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction --- 28 unchanged lines hidden (view full) --- 465system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 466system.cpu.op_class::total 5831 # Class of executed instruction 467system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 468system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 471system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 463system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states | 473system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states |
| 464system.membus.trans_dist::ReadReq 6078 # Transaction distribution 465system.membus.trans_dist::ReadResp 6088 # Transaction distribution 466system.membus.trans_dist::WriteReq 925 # Transaction distribution 467system.membus.trans_dist::WriteResp 925 # Transaction distribution 468system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 469system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 470system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 471system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 482system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 483system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram 484system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 485system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 486system.membus.snoop_fanout::min_value 0 # Request fanout histogram 487system.membus.snoop_fanout::max_value 0 # Request fanout histogram 488system.membus.snoop_fanout::total 7025 # Request fanout histogram 489system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) | 474system.membus.trans_dist::ReadReq 6078 # Transaction distribution 475system.membus.trans_dist::ReadResp 6088 # Transaction distribution 476system.membus.trans_dist::WriteReq 925 # Transaction distribution 477system.membus.trans_dist::WriteResp 925 # Transaction distribution 478system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 479system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 480system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 481system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 492system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 493system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram 494system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 495system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 496system.membus.snoop_fanout::min_value 0 # Request fanout histogram 497system.membus.snoop_fanout::max_value 0 # Request fanout histogram 498system.membus.snoop_fanout::total 7025 # Request fanout histogram 499system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) |
| 490system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 491system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) 492system.membus.respLayer0.utilization 3.4 # Layer utilization (%) 493system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) 494system.membus.respLayer1.utilization 1.0 # Layer utilization (%) | 500system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) 501system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) 502system.membus.respLayer0.utilization 3.1 # Layer utilization (%) 503system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) 504system.membus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 495 496---------- End Simulation Statistics ---------- | 505 506---------- End Simulation Statistics ---------- |