| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000326 # Number of seconds simulated 4sim_ticks 325849000 # Number of ticks simulated 5final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000326 # Number of seconds simulated 4sim_ticks 325849000 # Number of ticks simulated 5final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 204518 # Simulator instruction rate (inst/s) 8host_op_rate 236491 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13350749795 # Simulator tick rate (ticks/s) 10host_mem_usage 689808 # Number of bytes of host memory used | 7host_inst_rate 301831 # Simulator instruction rate (inst/s) 8host_op_rate 348968 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19697741357 # Simulator tick rate (ticks/s) 10host_mem_usage 691496 # Number of bytes of host memory used |
| 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4988 # Number of instructions simulated 13sim_ops 5770 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory 22system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory 23system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory --- 240 unchanged lines hidden (view full) --- 264system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) 265system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) 266system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) 267system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states 268system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states 269system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 270system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states 271system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory 22system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory 23system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory 24system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory --- 240 unchanged lines hidden (view full) --- 265system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) 266system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) 267system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) 268system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states 269system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states 270system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states 272system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 273system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states 274system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 272system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 293system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 294system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 295system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 296system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 297system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 298system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 299system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 300system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 275system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 296system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 297system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 298system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 301system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 302system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 303system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 304system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 301system.cpu.dtb.walker.walks 0 # Table walker walks requested 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 322system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.dtb.read_accesses 0 # DTB read accesses 325system.cpu.dtb.write_accesses 0 # DTB write accesses 326system.cpu.dtb.inst_accesses 0 # ITB inst accesses 327system.cpu.dtb.hits 0 # DTB hits 328system.cpu.dtb.misses 0 # DTB misses 329system.cpu.dtb.accesses 0 # DTB accesses | 305system.cpu.dtb.walker.walks 0 # Table walker walks requested 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 326system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 327system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 328system.cpu.dtb.read_accesses 0 # DTB read accesses 329system.cpu.dtb.write_accesses 0 # DTB write accesses 330system.cpu.dtb.inst_accesses 0 # ITB inst accesses 331system.cpu.dtb.hits 0 # DTB hits 332system.cpu.dtb.misses 0 # DTB misses 333system.cpu.dtb.accesses 0 # DTB accesses |
| 334system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 335system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 356system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 357system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 364system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 359system.cpu.itb.walker.walks 0 # Table walker walks requested 360system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 381system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.itb.read_accesses 0 # DTB read accesses 383system.cpu.itb.write_accesses 0 # DTB write accesses 384system.cpu.itb.inst_accesses 0 # ITB inst accesses 385system.cpu.itb.hits 0 # DTB hits 386system.cpu.itb.misses 0 # DTB misses 387system.cpu.itb.accesses 0 # DTB accesses 388system.cpu.workload.num_syscalls 13 # Number of system calls | 365system.cpu.itb.walker.walks 0 # Table walker walks requested 366system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 387system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu.itb.read_accesses 0 # DTB read accesses 389system.cpu.itb.write_accesses 0 # DTB write accesses 390system.cpu.itb.inst_accesses 0 # ITB inst accesses 391system.cpu.itb.hits 0 # DTB hits 392system.cpu.itb.misses 0 # DTB misses 393system.cpu.itb.accesses 0 # DTB accesses 394system.cpu.workload.num_syscalls 13 # Number of system calls |
| 395system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states |
|
| 389system.cpu.numCycles 325849 # number of cpu cycles simulated 390system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 391system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 392system.cpu.committedInsts 4988 # Number of instructions committed 393system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 394system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 395system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 396system.cpu.num_func_calls 215 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 441system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 442system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 443system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 444system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 445system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 446system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 447system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 448system.cpu.op_class::total 5831 # Class of executed instruction | 396system.cpu.numCycles 325849 # number of cpu cycles simulated 397system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 398system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 399system.cpu.committedInsts 4988 # Number of instructions committed 400system.cpu.committedOps 5770 # Number of ops (including micro ops) committed 401system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses 402system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 403system.cpu.num_func_calls 215 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 448system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction 449system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction 450system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction 451system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction 452system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction 453system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 454system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 455system.cpu.op_class::total 5831 # Class of executed instruction |
| 456system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states |
|
| 449system.membus.trans_dist::ReadReq 6078 # Transaction distribution 450system.membus.trans_dist::ReadResp 6088 # Transaction distribution 451system.membus.trans_dist::WriteReq 925 # Transaction distribution 452system.membus.trans_dist::WriteResp 925 # Transaction distribution 453system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 454system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 455system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 456system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) --- 24 unchanged lines hidden --- | 457system.membus.trans_dist::ReadReq 6078 # Transaction distribution 458system.membus.trans_dist::ReadResp 6088 # Transaction distribution 459system.membus.trans_dist::WriteReq 925 # Transaction distribution 460system.membus.trans_dist::WriteResp 925 # Transaction distribution 461system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 462system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 463system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 464system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) --- 24 unchanged lines hidden --- |