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2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000326 # Number of seconds simulated
4sim_ticks 325849000 # Number of ticks simulated
5final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 204518 # Simulator instruction rate (inst/s)
8host_op_rate 236491 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 13350749795 # Simulator tick rate (ticks/s)
10host_mem_usage 689808 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 4988 # Number of instructions simulated
13sim_ops 5770 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory
19system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory
20system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory
21system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory
22system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory
23system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory

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264system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ)
265system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ)
266system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW)
267system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states
268system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states
269system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
270system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states
271system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
272system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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293system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
294system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
295system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
296system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
297system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
298system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
299system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
300system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
301system.cpu.dtb.walker.walks 0 # Table walker walks requested
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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322system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
323system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
324system.cpu.dtb.read_accesses 0 # DTB read accesses
325system.cpu.dtb.write_accesses 0 # DTB write accesses
326system.cpu.dtb.inst_accesses 0 # ITB inst accesses
327system.cpu.dtb.hits 0 # DTB hits
328system.cpu.dtb.misses 0 # DTB misses
329system.cpu.dtb.accesses 0 # DTB accesses
330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
359system.cpu.itb.walker.walks 0 # Table walker walks requested
360system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
366system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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381system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
382system.cpu.itb.read_accesses 0 # DTB read accesses
383system.cpu.itb.write_accesses 0 # DTB write accesses
384system.cpu.itb.inst_accesses 0 # ITB inst accesses
385system.cpu.itb.hits 0 # DTB hits
386system.cpu.itb.misses 0 # DTB misses
387system.cpu.itb.accesses 0 # DTB accesses
388system.cpu.workload.num_syscalls 13 # Number of system calls
389system.cpu.numCycles 325849 # number of cpu cycles simulated
390system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
391system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
392system.cpu.committedInsts 4988 # Number of instructions committed
393system.cpu.committedOps 5770 # Number of ops (including micro ops) committed
394system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses
395system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
396system.cpu.num_func_calls 215 # number of times a function call or return occured

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441system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction
442system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction
443system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction
444system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction
445system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction
446system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
447system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
448system.cpu.op_class::total 5831 # Class of executed instruction
449system.membus.trans_dist::ReadReq 6078 # Transaction distribution
450system.membus.trans_dist::ReadResp 6088 # Transaction distribution
451system.membus.trans_dist::WriteReq 925 # Transaction distribution
452system.membus.trans_dist::WriteResp 925 # Transaction distribution
453system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
454system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
455system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
456system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes)

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