| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
| 26mem_ranges=0:536870911 | 26mem_ranges=0:536870911:0:0:0:0 |
| 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags | 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 60 unchanged lines hidden (view full) --- 95tracer=system.cpu.tracer 96workload=system.cpu.workload 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags |
| 103addr_ranges=0:18446744073709551615 | 103addr_ranges=0:18446744073709551615:0:0:0:0 |
| 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=AlphaTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags | 104assoc=2 105clk_domain=system.clk_domain 106clusivity=mostly_incl 107default_p_state=UNDEFINED 108demand_mshr_reserve=1 109eventq_index=0 110hit_latency=2 111is_read_only=false --- 34 unchanged lines hidden (view full) --- 146[system.cpu.dtb] 147type=AlphaTLB 148eventq_index=0 149size=64 150 151[system.cpu.icache] 152type=Cache 153children=tags |
| 154addr_ranges=0:18446744073709551615 | 154addr_ranges=0:18446744073709551615:0:0:0:0 |
| 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 107 unchanged lines hidden (view full) --- 270eventq_index=0 271lookup_latency=0 272max_capacity=8388608 273system=system 274 275[system.l2cache] 276type=Cache 277children=tags | 155assoc=2 156clk_domain=system.clk_domain 157clusivity=mostly_incl 158default_p_state=UNDEFINED 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false --- 107 unchanged lines hidden (view full) --- 270eventq_index=0 271lookup_latency=0 272max_capacity=8388608 273system=system 274 275[system.l2cache] 276type=Cache 277children=tags |
| 278addr_ranges=0:18446744073709551615 | 278addr_ranges=0:18446744073709551615:0:0:0:0 |
| 279assoc=8 280clk_domain=system.clk_domain 281clusivity=mostly_incl 282default_p_state=UNDEFINED 283demand_mshr_reserve=1 284eventq_index=0 285hit_latency=20 286is_read_only=false --- 28 unchanged lines hidden (view full) --- 315p_state_clk_gate_max=1000000000000 316p_state_clk_gate_min=1000 317power_model=Null 318sequential_access=false 319size=262144 320 321[system.mem_ctrl] 322type=DRAMCtrl | 279assoc=8 280clk_domain=system.clk_domain 281clusivity=mostly_incl 282default_p_state=UNDEFINED 283demand_mshr_reserve=1 284eventq_index=0 285hit_latency=20 286is_read_only=false --- 28 unchanged lines hidden (view full) --- 315p_state_clk_gate_max=1000000000000 316p_state_clk_gate_min=1000 317power_model=Null 318sequential_access=false 319size=262144 320 321[system.mem_ctrl] 322type=DRAMCtrl |
| 323IDD0=0.075000 | 323IDD0=0.055000 |
| 324IDD02=0.000000 | 324IDD02=0.000000 |
| 325IDD2N=0.050000 | 325IDD2N=0.032000 |
| 326IDD2N2=0.000000 327IDD2P0=0.000000 328IDD2P02=0.000000 | 326IDD2N2=0.000000 327IDD2P0=0.000000 328IDD2P02=0.000000 |
| 329IDD2P1=0.000000 | 329IDD2P1=0.032000 |
| 330IDD2P12=0.000000 | 330IDD2P12=0.000000 |
| 331IDD3N=0.057000 | 331IDD3N=0.038000 |
| 332IDD3N2=0.000000 333IDD3P0=0.000000 334IDD3P02=0.000000 | 332IDD3N2=0.000000 333IDD3P0=0.000000 334IDD3P02=0.000000 |
| 335IDD3P1=0.000000 | 335IDD3P1=0.038000 |
| 336IDD3P12=0.000000 | 336IDD3P12=0.000000 |
| 337IDD4R=0.187000 | 337IDD4R=0.157000 |
| 338IDD4R2=0.000000 | 338IDD4R2=0.000000 |
| 339IDD4W=0.165000 | 339IDD4W=0.125000 |
| 340IDD4W2=0.000000 | 340IDD4W2=0.000000 |
| 341IDD5=0.220000 | 341IDD5=0.235000 |
| 342IDD52=0.000000 | 342IDD52=0.000000 |
| 343IDD6=0.000000 | 343IDD6=0.020000 |
| 344IDD62=0.000000 345VDD=1.500000 346VDD2=0.000000 347activation_limit=4 348addr_mapping=RoRaBaCoCh 349bank_groups_per_rank=0 350banks_per_rank=8 351burst_length=8 352channels=1 353clk_domain=system.clk_domain 354conf_table_reported=true 355default_p_state=UNDEFINED 356device_bus_width=8 357device_rowbuffer_size=1024 358device_size=536870912 359devices_per_rank=8 360dll=true 361eventq_index=0 362in_addr_map=true | 344IDD62=0.000000 345VDD=1.500000 346VDD2=0.000000 347activation_limit=4 348addr_mapping=RoRaBaCoCh 349bank_groups_per_rank=0 350banks_per_rank=8 351burst_length=8 352channels=1 353clk_domain=system.clk_domain 354conf_table_reported=true 355default_p_state=UNDEFINED 356device_bus_width=8 357device_rowbuffer_size=1024 358device_size=536870912 359devices_per_rank=8 360dll=true 361eventq_index=0 362in_addr_map=true |
| 363kvm_map=true |
|
| 363max_accesses_per_row=16 364mem_sched_policy=frfcfs 365min_writes_per_switch=16 366null=false 367p_state_clk_gate_bins=20 368p_state_clk_gate_max=1000000000000 369p_state_clk_gate_min=1000 370page_policy=open_adaptive 371power_model=Null | 364max_accesses_per_row=16 365mem_sched_policy=frfcfs 366min_writes_per_switch=16 367null=false 368p_state_clk_gate_bins=20 369p_state_clk_gate_max=1000000000000 370p_state_clk_gate_min=1000 371page_policy=open_adaptive 372power_model=Null |
| 372range=0:536870911 | 373range=0:536870911:0:0:0:0 |
| 373ranks_per_channel=2 374read_buffer_size=32 375static_backend_latency=10000 376static_frontend_latency=10000 377tBURST=5000 378tCCD_L=0 379tCK=1250 380tCL=13750 --- 5 unchanged lines hidden (view full) --- 386tRP=13750 387tRRD=6000 388tRRD_L=0 389tRTP=7500 390tRTW=2500 391tWR=15000 392tWTR=7500 393tXAW=30000 | 374ranks_per_channel=2 375read_buffer_size=32 376static_backend_latency=10000 377static_frontend_latency=10000 378tBURST=5000 379tCCD_L=0 380tCK=1250 381tCL=13750 --- 5 unchanged lines hidden (view full) --- 387tRP=13750 388tRRD=6000 389tRRD_L=0 390tRTP=7500 391tRTW=2500 392tWR=15000 393tWTR=7500 394tXAW=30000 |
| 394tXP=0 | 395tXP=6000 |
| 395tXPDLL=0 | 396tXPDLL=0 |
| 396tXS=0 | 397tXS=270000 |
| 397tXSDLL=0 398write_buffer_size=64 399write_high_thresh_perc=85 400write_low_thresh_perc=50 401port=system.membus.master[0] 402 403[system.membus] 404type=CoherentXBar | 398tXSDLL=0 399write_buffer_size=64 400write_high_thresh_perc=85 401write_low_thresh_perc=50 402port=system.membus.master[0] 403 404[system.membus] 405type=CoherentXBar |
| 406children=snoop_filter |
|
| 405clk_domain=system.clk_domain 406default_p_state=UNDEFINED 407eventq_index=0 408forward_latency=4 409frontend_latency=3 410p_state_clk_gate_bins=20 411p_state_clk_gate_max=1000000000000 412p_state_clk_gate_min=1000 413point_of_coherency=true 414power_model=Null 415response_latency=2 | 407clk_domain=system.clk_domain 408default_p_state=UNDEFINED 409eventq_index=0 410forward_latency=4 411frontend_latency=3 412p_state_clk_gate_bins=20 413p_state_clk_gate_max=1000000000000 414p_state_clk_gate_min=1000 415point_of_coherency=true 416power_model=Null 417response_latency=2 |
| 416snoop_filter=Null | 418snoop_filter=system.membus.snoop_filter |
| 417snoop_response_latency=4 418system=system 419use_default_range=false 420width=16 421master=system.mem_ctrl.port 422slave=system.l2cache.mem_side system.system_port 423 | 419snoop_response_latency=4 420system=system 421use_default_range=false 422width=16 423master=system.mem_ctrl.port 424slave=system.l2cache.mem_side system.system_port 425 |
| 426[system.membus.snoop_filter] 427type=SnoopFilter 428eventq_index=0 429lookup_latency=1 430max_capacity=8388608 431system=system 432 |
|