1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=0:536870911
27memories=system.mem_ctrl
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null
35readfile=
36symbolfile=
37thermal_components=
38thermal_model=Null
39work_begin_ckpt_count=0
40work_begin_cpu_id_exit=-1
41work_begin_exit_count=0
42work_cpus_ckpt_count=0
--- 18 unchanged lines hidden (view full) ---
61
62[system.cpu]
63type=TimingSimpleCPU
64children=dcache dtb icache interrupts isa itb tracer workload
65branchPred=Null
66checker=Null
67clk_domain=system.clk_domain
68cpu_id=-1
69default_p_state=UNDEFINED
70do_checkpoint_insts=true
71do_quiesce=true
72do_statistics_insts=true
73dtb=system.cpu.dtb
74eventq_index=0
75function_trace=false
76function_trace_start=0
77interrupts=system.cpu.interrupts
78isa=system.cpu.isa
79itb=system.cpu.itb
80max_insts_all_threads=0
81max_insts_any_thread=0
82max_loads_all_threads=0
83max_loads_any_thread=0
84numThreads=1
85p_state_clk_gate_bins=20
86p_state_clk_gate_max=1000000000000
87p_state_clk_gate_min=1000
88power_model=Null
89profile=0
90progress_interval=0
91simpoint_start_insts=
92socket_id=0
93switched_out=false
94system=system
95tracer=system.cpu.tracer
96workload=system.cpu.workload
97dcache_port=system.cpu.dcache.cpu_side
98icache_port=system.cpu.icache.cpu_side
99
100[system.cpu.dcache]
101type=Cache
102children=tags
103addr_ranges=0:18446744073709551615
104assoc=2
105clk_domain=system.clk_domain
106clusivity=mostly_incl
107default_p_state=UNDEFINED
108demand_mshr_reserve=1
109eventq_index=0
110hit_latency=2
111is_read_only=false
112max_miss_count=0
113mshrs=4
114p_state_clk_gate_bins=20
115p_state_clk_gate_max=1000000000000
116p_state_clk_gate_min=1000
117power_model=Null
118prefetch_on_access=false
119prefetcher=Null
120response_latency=2
121sequential_access=false
122size=65536
123system=system
124tags=system.cpu.dcache.tags
125tgts_per_mshr=20
126write_buffers=8
127writeback_clean=false
128cpu_side=system.cpu.dcache_port
129mem_side=system.l2bus.slave[1]
130
131[system.cpu.dcache.tags]
132type=LRU
133assoc=2
134block_size=64
135clk_domain=system.clk_domain
136default_p_state=UNDEFINED
137eventq_index=0
138hit_latency=2
139p_state_clk_gate_bins=20
140p_state_clk_gate_max=1000000000000
141p_state_clk_gate_min=1000
142power_model=Null
143sequential_access=false
144size=65536
145
146[system.cpu.dtb]
147type=AlphaTLB
148eventq_index=0
149size=64
150
151[system.cpu.icache]
152type=Cache
153children=tags
154addr_ranges=0:18446744073709551615
155assoc=2
156clk_domain=system.clk_domain
157clusivity=mostly_incl
158default_p_state=UNDEFINED
159demand_mshr_reserve=1
160eventq_index=0
161hit_latency=2
162is_read_only=false
163max_miss_count=0
164mshrs=4
165p_state_clk_gate_bins=20
166p_state_clk_gate_max=1000000000000
167p_state_clk_gate_min=1000
168power_model=Null
169prefetch_on_access=false
170prefetcher=Null
171response_latency=2
172sequential_access=false
173size=16384
174system=system
175tags=system.cpu.icache.tags
176tgts_per_mshr=20
177write_buffers=8
178writeback_clean=false
179cpu_side=system.cpu.icache_port
180mem_side=system.l2bus.slave[0]
181
182[system.cpu.icache.tags]
183type=LRU
184assoc=2
185block_size=64
186clk_domain=system.clk_domain
187default_p_state=UNDEFINED
188eventq_index=0
189hit_latency=2
190p_state_clk_gate_bins=20
191p_state_clk_gate_max=1000000000000
192p_state_clk_gate_min=1000
193power_model=Null
194sequential_access=false
195size=16384
196
197[system.cpu.interrupts]
198type=AlphaInterrupts
199eventq_index=0
200
201[system.cpu.isa]
--- 40 unchanged lines hidden (view full) ---
242eventq_index=0
243sys_clk_domain=system.clk_domain
244transition_latency=100000000
245
246[system.l2bus]
247type=CoherentXBar
248children=snoop_filter
249clk_domain=system.clk_domain
250default_p_state=UNDEFINED
251eventq_index=0
252forward_latency=0
253frontend_latency=1
254p_state_clk_gate_bins=20
255p_state_clk_gate_max=1000000000000
256p_state_clk_gate_min=1000
257point_of_coherency=false
258power_model=Null
259response_latency=1
260snoop_filter=system.l2bus.snoop_filter
261snoop_response_latency=1
262system=system
263use_default_range=false
264width=32
265master=system.l2cache.cpu_side
266slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 7 unchanged lines hidden (view full) ---
274
275[system.l2cache]
276type=Cache
277children=tags
278addr_ranges=0:18446744073709551615
279assoc=8
280clk_domain=system.clk_domain
281clusivity=mostly_incl
282default_p_state=UNDEFINED
283demand_mshr_reserve=1
284eventq_index=0
285hit_latency=20
286is_read_only=false
287max_miss_count=0
288mshrs=20
289p_state_clk_gate_bins=20
290p_state_clk_gate_max=1000000000000
291p_state_clk_gate_min=1000
292power_model=Null
293prefetch_on_access=false
294prefetcher=Null
295response_latency=20
296sequential_access=false
297size=262144
298system=system
299tags=system.l2cache.tags
300tgts_per_mshr=12
301write_buffers=8
302writeback_clean=false
303cpu_side=system.l2bus.master[0]
304mem_side=system.membus.slave[0]
305
306[system.l2cache.tags]
307type=LRU
308assoc=8
309block_size=64
310clk_domain=system.clk_domain
311default_p_state=UNDEFINED
312eventq_index=0
313hit_latency=20
314p_state_clk_gate_bins=20
315p_state_clk_gate_max=1000000000000
316p_state_clk_gate_min=1000
317power_model=Null
318sequential_access=false
319size=262144
320
321[system.mem_ctrl]
322type=DRAMCtrl
323IDD0=0.075000
324IDD02=0.000000
325IDD2N=0.050000
--- 21 unchanged lines hidden (view full) ---
347activation_limit=4
348addr_mapping=RoRaBaCoCh
349bank_groups_per_rank=0
350banks_per_rank=8
351burst_length=8
352channels=1
353clk_domain=system.clk_domain
354conf_table_reported=true
355default_p_state=UNDEFINED
356device_bus_width=8
357device_rowbuffer_size=1024
358device_size=536870912
359devices_per_rank=8
360dll=true
361eventq_index=0
362in_addr_map=true
363max_accesses_per_row=16
364mem_sched_policy=frfcfs
365min_writes_per_switch=16
366null=false
367p_state_clk_gate_bins=20
368p_state_clk_gate_max=1000000000000
369p_state_clk_gate_min=1000
370page_policy=open_adaptive
371power_model=Null
372range=0:536870911
373ranks_per_channel=2
374read_buffer_size=32
375static_backend_latency=10000
376static_frontend_latency=10000
377tBURST=5000
378tCCD_L=0
379tCK=1250
--- 18 unchanged lines hidden (view full) ---
398write_buffer_size=64
399write_high_thresh_perc=85
400write_low_thresh_perc=50
401port=system.membus.master[0]
402
403[system.membus]
404type=CoherentXBar
405clk_domain=system.clk_domain
406default_p_state=UNDEFINED
407eventq_index=0
408forward_latency=4
409frontend_latency=3
410p_state_clk_gate_bins=20
411p_state_clk_gate_max=1000000000000
412p_state_clk_gate_min=1000
413point_of_coherency=true
414power_model=Null
415response_latency=2
416snoop_filter=Null
417snoop_response_latency=4
418system=system
419use_default_range=false
420width=16
421master=system.mem_ctrl.port
422slave=system.l2cache.mem_side system.system_port
423
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=0:536870911
27memories=system.mem_ctrl
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null
35readfile=
36symbolfile=
37thermal_components=
38thermal_model=Null
39work_begin_ckpt_count=0
40work_begin_cpu_id_exit=-1
41work_begin_exit_count=0
42work_cpus_ckpt_count=0
--- 18 unchanged lines hidden (view full) ---
61
62[system.cpu]
63type=TimingSimpleCPU
64children=dcache dtb icache interrupts isa itb tracer workload
65branchPred=Null
66checker=Null
67clk_domain=system.clk_domain
68cpu_id=-1
69default_p_state=UNDEFINED
70do_checkpoint_insts=true
71do_quiesce=true
72do_statistics_insts=true
73dtb=system.cpu.dtb
74eventq_index=0
75function_trace=false
76function_trace_start=0
77interrupts=system.cpu.interrupts
78isa=system.cpu.isa
79itb=system.cpu.itb
80max_insts_all_threads=0
81max_insts_any_thread=0
82max_loads_all_threads=0
83max_loads_any_thread=0
84numThreads=1
85p_state_clk_gate_bins=20
86p_state_clk_gate_max=1000000000000
87p_state_clk_gate_min=1000
88power_model=Null
89profile=0
90progress_interval=0
91simpoint_start_insts=
92socket_id=0
93switched_out=false
94system=system
95tracer=system.cpu.tracer
96workload=system.cpu.workload
97dcache_port=system.cpu.dcache.cpu_side
98icache_port=system.cpu.icache.cpu_side
99
100[system.cpu.dcache]
101type=Cache
102children=tags
103addr_ranges=0:18446744073709551615
104assoc=2
105clk_domain=system.clk_domain
106clusivity=mostly_incl
107default_p_state=UNDEFINED
108demand_mshr_reserve=1
109eventq_index=0
110hit_latency=2
111is_read_only=false
112max_miss_count=0
113mshrs=4
114p_state_clk_gate_bins=20
115p_state_clk_gate_max=1000000000000
116p_state_clk_gate_min=1000
117power_model=Null
118prefetch_on_access=false
119prefetcher=Null
120response_latency=2
121sequential_access=false
122size=65536
123system=system
124tags=system.cpu.dcache.tags
125tgts_per_mshr=20
126write_buffers=8
127writeback_clean=false
128cpu_side=system.cpu.dcache_port
129mem_side=system.l2bus.slave[1]
130
131[system.cpu.dcache.tags]
132type=LRU
133assoc=2
134block_size=64
135clk_domain=system.clk_domain
136default_p_state=UNDEFINED
137eventq_index=0
138hit_latency=2
139p_state_clk_gate_bins=20
140p_state_clk_gate_max=1000000000000
141p_state_clk_gate_min=1000
142power_model=Null
143sequential_access=false
144size=65536
145
146[system.cpu.dtb]
147type=AlphaTLB
148eventq_index=0
149size=64
150
151[system.cpu.icache]
152type=Cache
153children=tags
154addr_ranges=0:18446744073709551615
155assoc=2
156clk_domain=system.clk_domain
157clusivity=mostly_incl
158default_p_state=UNDEFINED
159demand_mshr_reserve=1
160eventq_index=0
161hit_latency=2
162is_read_only=false
163max_miss_count=0
164mshrs=4
165p_state_clk_gate_bins=20
166p_state_clk_gate_max=1000000000000
167p_state_clk_gate_min=1000
168power_model=Null
169prefetch_on_access=false
170prefetcher=Null
171response_latency=2
172sequential_access=false
173size=16384
174system=system
175tags=system.cpu.icache.tags
176tgts_per_mshr=20
177write_buffers=8
178writeback_clean=false
179cpu_side=system.cpu.icache_port
180mem_side=system.l2bus.slave[0]
181
182[system.cpu.icache.tags]
183type=LRU
184assoc=2
185block_size=64
186clk_domain=system.clk_domain
187default_p_state=UNDEFINED
188eventq_index=0
189hit_latency=2
190p_state_clk_gate_bins=20
191p_state_clk_gate_max=1000000000000
192p_state_clk_gate_min=1000
193power_model=Null
194sequential_access=false
195size=16384
196
197[system.cpu.interrupts]
198type=AlphaInterrupts
199eventq_index=0
200
201[system.cpu.isa]
--- 40 unchanged lines hidden (view full) ---
242eventq_index=0
243sys_clk_domain=system.clk_domain
244transition_latency=100000000
245
246[system.l2bus]
247type=CoherentXBar
248children=snoop_filter
249clk_domain=system.clk_domain
250default_p_state=UNDEFINED
251eventq_index=0
252forward_latency=0
253frontend_latency=1
254p_state_clk_gate_bins=20
255p_state_clk_gate_max=1000000000000
256p_state_clk_gate_min=1000
257point_of_coherency=false
258power_model=Null
259response_latency=1
260snoop_filter=system.l2bus.snoop_filter
261snoop_response_latency=1
262system=system
263use_default_range=false
264width=32
265master=system.l2cache.cpu_side
266slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 7 unchanged lines hidden (view full) ---
274
275[system.l2cache]
276type=Cache
277children=tags
278addr_ranges=0:18446744073709551615
279assoc=8
280clk_domain=system.clk_domain
281clusivity=mostly_incl
282default_p_state=UNDEFINED
283demand_mshr_reserve=1
284eventq_index=0
285hit_latency=20
286is_read_only=false
287max_miss_count=0
288mshrs=20
289p_state_clk_gate_bins=20
290p_state_clk_gate_max=1000000000000
291p_state_clk_gate_min=1000
292power_model=Null
293prefetch_on_access=false
294prefetcher=Null
295response_latency=20
296sequential_access=false
297size=262144
298system=system
299tags=system.l2cache.tags
300tgts_per_mshr=12
301write_buffers=8
302writeback_clean=false
303cpu_side=system.l2bus.master[0]
304mem_side=system.membus.slave[0]
305
306[system.l2cache.tags]
307type=LRU
308assoc=8
309block_size=64
310clk_domain=system.clk_domain
311default_p_state=UNDEFINED
312eventq_index=0
313hit_latency=20
314p_state_clk_gate_bins=20
315p_state_clk_gate_max=1000000000000
316p_state_clk_gate_min=1000
317power_model=Null
318sequential_access=false
319size=262144
320
321[system.mem_ctrl]
322type=DRAMCtrl
323IDD0=0.075000
324IDD02=0.000000
325IDD2N=0.050000
--- 21 unchanged lines hidden (view full) ---
347activation_limit=4
348addr_mapping=RoRaBaCoCh
349bank_groups_per_rank=0
350banks_per_rank=8
351burst_length=8
352channels=1
353clk_domain=system.clk_domain
354conf_table_reported=true
355default_p_state=UNDEFINED
356device_bus_width=8
357device_rowbuffer_size=1024
358device_size=536870912
359devices_per_rank=8
360dll=true
361eventq_index=0
362in_addr_map=true
363max_accesses_per_row=16
364mem_sched_policy=frfcfs
365min_writes_per_switch=16
366null=false
367p_state_clk_gate_bins=20
368p_state_clk_gate_max=1000000000000
369p_state_clk_gate_min=1000
370page_policy=open_adaptive
371power_model=Null
372range=0:536870911
373ranks_per_channel=2
374read_buffer_size=32
375static_backend_latency=10000
376static_frontend_latency=10000
377tBURST=5000
378tCCD_L=0
379tCK=1250
--- 18 unchanged lines hidden (view full) ---
398write_buffer_size=64
399write_high_thresh_perc=85
400write_low_thresh_perc=50
401port=system.membus.master[0]
402
403[system.membus]
404type=CoherentXBar
405clk_domain=system.clk_domain
406default_p_state=UNDEFINED
407eventq_index=0
408forward_latency=4
409frontend_latency=3
410p_state_clk_gate_bins=20
411p_state_clk_gate_max=1000000000000
412p_state_clk_gate_min=1000
413point_of_coherency=true
414power_model=Null
415response_latency=2
416snoop_filter=Null
417snoop_response_latency=4
418system=system
419use_default_range=false
420width=16
421master=system.mem_ctrl.port
422slave=system.l2cache.mem_side system.system_port
423