1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
26mem_ranges=0:536870911:0:0:0:0 |
27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 113 unchanged lines hidden (view full) --- 148domains= 149enable=false 150eventq_index=0 151sys_clk_domain=system.clk_domain 152transition_latency=100000000 153 154[system.mem_ctrl] 155type=DRAMCtrl |
156IDD0=0.055000 |
157IDD02=0.000000 |
158IDD2N=0.032000 |
159IDD2N2=0.000000 160IDD2P0=0.000000 161IDD2P02=0.000000 |
162IDD2P1=0.032000 |
163IDD2P12=0.000000 |
164IDD3N=0.038000 |
165IDD3N2=0.000000 166IDD3P0=0.000000 167IDD3P02=0.000000 |
168IDD3P1=0.038000 |
169IDD3P12=0.000000 |
170IDD4R=0.157000 |
171IDD4R2=0.000000 |
172IDD4W=0.125000 |
173IDD4W2=0.000000 |
174IDD5=0.235000 |
175IDD52=0.000000 |
176IDD6=0.020000 |
177IDD62=0.000000 178VDD=1.500000 179VDD2=0.000000 180activation_limit=4 181addr_mapping=RoRaBaCoCh 182bank_groups_per_rank=0 183banks_per_rank=8 184burst_length=8 185channels=1 186clk_domain=system.clk_domain 187conf_table_reported=true 188default_p_state=UNDEFINED 189device_bus_width=8 190device_rowbuffer_size=1024 191device_size=536870912 192devices_per_rank=8 193dll=true 194eventq_index=0 195in_addr_map=true |
196kvm_map=true |
197max_accesses_per_row=16 198mem_sched_policy=frfcfs 199min_writes_per_switch=16 200null=false 201p_state_clk_gate_bins=20 202p_state_clk_gate_max=1000000000000 203p_state_clk_gate_min=1000 204page_policy=open_adaptive 205power_model=Null |
206range=0:536870911:0:0:0:0 |
207ranks_per_channel=2 208read_buffer_size=32 209static_backend_latency=10000 210static_frontend_latency=10000 211tBURST=5000 212tCCD_L=0 213tCK=1250 214tCL=13750 --- 5 unchanged lines hidden (view full) --- 220tRP=13750 221tRRD=6000 222tRRD_L=0 223tRTP=7500 224tRTW=2500 225tWR=15000 226tWTR=7500 227tXAW=30000 |
228tXP=6000 |
229tXPDLL=0 |
230tXS=270000 |
231tXSDLL=0 232write_buffer_size=64 233write_high_thresh_perc=85 234write_low_thresh_perc=50 235port=system.membus.master[0] 236 237[system.membus] 238type=CoherentXBar |
239children=snoop_filter |
240clk_domain=system.clk_domain 241default_p_state=UNDEFINED 242eventq_index=0 243forward_latency=4 244frontend_latency=3 245p_state_clk_gate_bins=20 246p_state_clk_gate_max=1000000000000 247p_state_clk_gate_min=1000 248point_of_coherency=true 249power_model=Null 250response_latency=2 |
251snoop_filter=system.membus.snoop_filter |
252snoop_response_latency=4 253system=system 254use_default_range=false 255width=16 256master=system.mem_ctrl.port 257slave=system.cpu.icache_port system.cpu.dcache_port system.system_port 258 |
259[system.membus.snoop_filter] 260type=SnoopFilter 261eventq_index=0 262lookup_latency=1 263max_capacity=8388608 264system=system 265 |