| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000042 # Number of seconds simulated 4sim_ticks 41800000 # Number of ticks simulated 5final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000042 # Number of seconds simulated 4sim_ticks 41800000 # Number of ticks simulated 5final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 399467 # Simulator instruction rate (inst/s) 8host_op_rate 399277 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1099343547 # Simulator tick rate (ticks/s) 10host_mem_usage 210560 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host | 7host_inst_rate 130693 # Simulator instruction rate (inst/s) 8host_op_rate 130661 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 359830859 # Simulator tick rate (ticks/s) 10host_mem_usage 220580 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host |
| 12sim_insts 15175 # Number of instructions simulated 13sim_ops 15175 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 26624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 416 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 61 unchanged lines hidden (view full) --- 81system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses 82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency 83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency 84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency 85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 15175 # Number of instructions simulated 13sim_ops 15175 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 26624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 416 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 61 unchanged lines hidden (view full) --- 81system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses 82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency 83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency 84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency 85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 89system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 90system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 89system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 91system.cpu.icache.fast_writes 0 # number of fast writes performed 92system.cpu.icache.cache_copies 0 # number of cache copies performed 93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 94system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 95system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 96system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 97system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 98system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses --- 62 unchanged lines hidden (view full) --- 161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 165system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 166system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 167system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 91system.cpu.icache.fast_writes 0 # number of fast writes performed 92system.cpu.icache.cache_copies 0 # number of cache copies performed 93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 94system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 95system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 96system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 97system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 98system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses --- 62 unchanged lines hidden (view full) --- 161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 165system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 166system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 167system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 169system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 169system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 171system.cpu.dcache.fast_writes 0 # number of fast writes performed 172system.cpu.dcache.cache_copies 0 # number of cache copies performed 173system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 174system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 176system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 177system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 178system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 258system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 259system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 262system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 171system.cpu.dcache.fast_writes 0 # number of fast writes performed 172system.cpu.dcache.cache_copies 0 # number of cache copies performed 173system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 174system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 176system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 177system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 178system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 258system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 259system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 262system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 266system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 267system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 266system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 268system.cpu.l2cache.fast_writes 0 # number of fast writes performed 269system.cpu.l2cache.cache_copies 0 # number of cache copies performed 270system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 271system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 272system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses 273system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 274system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 275system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 268system.cpu.l2cache.fast_writes 0 # number of fast writes performed 269system.cpu.l2cache.cache_copies 0 # number of cache copies performed 270system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 271system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 272system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses 273system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 274system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 275system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |