| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000044 # Number of seconds simulated 4sim_ticks 44282500 # Number of ticks simulated 5final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000044 # Number of seconds simulated 4sim_ticks 44282500 # Number of ticks simulated 5final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 282453 # Simulator instruction rate (inst/s) 8host_op_rate 282325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 824249311 # Simulator tick rate (ticks/s) 10host_mem_usage 245052 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 533053 # Simulator instruction rate (inst/s) 8host_op_rate 532883 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1555927955 # Simulator tick rate (ticks/s) 10host_mem_usage 289976 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 18 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.workload.num_syscalls 18 # Number of system calls |
| 36system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.numCycles 88565 # number of cpu cycles simulated 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 15162 # Number of instructions committed 38system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 41system.cpu.num_func_calls 385 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 84system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction 87system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction 88system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 15207 # Class of executed instruction | 37system.cpu.numCycles 88565 # number of cpu cycles simulated 38system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40system.cpu.committedInsts 15162 # Number of instructions committed 41system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 42system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 43system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 44system.cpu.num_func_calls 385 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction 90system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction 91system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 15207 # Class of executed instruction |
| 95system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 92system.cpu.dcache.tags.replacements 0 # number of replacements 93system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use 94system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor 99system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 104system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 105system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 106system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses | 96system.cpu.dcache.tags.replacements 0 # number of replacements 97system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use 98system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 99system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 100system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 101system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 102system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor 103system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy 105system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 107system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 108system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 109system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 110system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses |
| 111system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 107system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits 108system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits 109system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits 110system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits 111system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 112system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 113system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits 114system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits --- 74 unchanged lines hidden (view full) --- 189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 191system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 193system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 112system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits 113system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits 114system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits 116system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 117system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 118system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits 119system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits --- 74 unchanged lines hidden (view full) --- 194system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 195system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 196system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 197system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 198system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 199system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 200system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 201system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 202system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 197system.cpu.icache.tags.replacements 0 # number of replacements 198system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use 199system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 200system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 201system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 202system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 203system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor 204system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy 205system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy 206system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 207system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 208system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 209system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 210system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 211system.cpu.icache.tags.data_accesses 30696 # Number of data accesses | 203system.cpu.icache.tags.replacements 0 # number of replacements 204system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use 205system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 206system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 207system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 208system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 209system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor 210system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy 211system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy 212system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 214system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 215system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 216system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 217system.cpu.icache.tags.data_accesses 30696 # Number of data accesses |
| 218system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 212system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits 213system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits 214system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits 215system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits 216system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 217system.cpu.icache.overall_hits::total 14928 # number of overall hits 218system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 219system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 270system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 271system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 272system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency 273system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency 274system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 275system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 276system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 277system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency | 219system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits 220system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits 221system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits 222system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits 223system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 224system.cpu.icache.overall_hits::total 14928 # number of overall hits 225system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 226system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 278system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency 280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 282system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 284system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency |
| 285system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 278system.cpu.l2cache.tags.replacements 0 # number of replacements 279system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use 280system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 281system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 282system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 283system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 284system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor 285system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor 286system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy 287system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy 288system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy 289system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 290system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 291system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 292system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 293system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 294system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses | 286system.cpu.l2cache.tags.replacements 0 # number of replacements 287system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use 288system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 289system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 290system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 291system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 292system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 298system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 299system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 300system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 301system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 302system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses |
| 303system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 295system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 296system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 297system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 298system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 299system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 300system.cpu.l2cache.overall_hits::total 2 # number of overall hits 301system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses 302system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 413system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 414system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 415system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 416system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 417system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 418system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 419system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 420system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 304system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 305system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 306system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 307system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 308system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 309system.cpu.l2cache.overall_hits::total 2 # number of overall hits 310system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses 311system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 424system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 430system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
|
| 421system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 422system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 423system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution 426system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 427system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 428system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 442system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 443system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 444system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 445system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 446system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 447system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 448system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 449system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) | 431system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution 436system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 452system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 454system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 455system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 456system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 457system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 460system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states |
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| 450system.membus.trans_dist::ReadResp 331 # Transaction distribution 451system.membus.trans_dist::ReadExReq 85 # Transaction distribution 452system.membus.trans_dist::ReadExResp 85 # Transaction distribution 453system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution 454system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 455system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 456system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 457system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 461system.membus.trans_dist::ReadResp 331 # Transaction distribution 462system.membus.trans_dist::ReadExReq 85 # Transaction distribution 463system.membus.trans_dist::ReadExResp 85 # Transaction distribution 464system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution 465system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 466system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 467system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 468system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |