| stats.txt (11312:3d7a85d71bd1) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000044 # Number of seconds simulated 4sim_ticks 44282500 # Number of ticks simulated 5final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000044 # Number of seconds simulated 4sim_ticks 44282500 # Number of ticks simulated 5final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 17930 # Simulator instruction rate (inst/s) 8host_op_rate 17930 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52364992 # Simulator tick rate (ticks/s) 10host_mem_usage 228848 # Number of bytes of host memory used 11host_seconds 0.85 # Real time elapsed on the host | 7host_inst_rate 298703 # Simulator instruction rate (inst/s) 8host_op_rate 298583 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 871748609 # Simulator tick rate (ticks/s) 10host_mem_usage 249440 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 137 unchanged lines hidden (view full) --- 157system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 158system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 159system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 160system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 161system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 164system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 137 unchanged lines hidden (view full) --- 157system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 158system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 159system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 160system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 161system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 162system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 163system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 164system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 165system.cpu.dcache.fast_writes 0 # number of fast writes performed 166system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 167system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 168system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 169system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 170system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 171system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 172system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 173system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 174system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 196system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 198system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 165system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 166system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses 167system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses 168system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses 169system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 170system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 171system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 172system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 191system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 193system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 199system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 200system.cpu.icache.tags.replacements 0 # number of replacements 201system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use 202system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 203system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 204system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 205system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 206system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor 207system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 197system.cpu.icache.tags.replacements 0 # number of replacements 198system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use 199system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 200system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 201system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 202system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 203system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor 204system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 246system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency 247system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency 248system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 249system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 250system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 251system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 252system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 253system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 257system.cpu.icache.fast_writes 0 # number of fast writes performed 258system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 260system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 261system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 262system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 263system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 264system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 276system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency 278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 280system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 282system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency | 254system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 255system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 256system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 257system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 258system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 259system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 260system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles 261system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 270system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 271system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses 272system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency 273system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency 274system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 275system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency 276system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency 277system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency |
| 283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 284system.cpu.l2cache.tags.replacements 0 # number of replacements 285system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use 286system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 287system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 288system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 289system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 290system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor 291system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 365system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 366system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency 367system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 368system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 369system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 370system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 278system.cpu.l2cache.tags.replacements 0 # number of replacements 279system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use 280system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 281system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 282system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 283system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 284system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor 285system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 359system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 360system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency 361system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 365system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 366system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 373system.cpu.l2cache.fast_writes 0 # number of fast writes performed 374system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 375system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 376system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 377system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 378system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 379system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 380system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 381system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 382system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency | 367system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses 368system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses 369system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 370system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 371system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses 372system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses 373system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 374system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 407system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 408system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 409system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 410system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 411system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency 412system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 413system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 414system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency |
| 423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 424system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 430system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution --- 52 unchanged lines hidden --- | 415system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 416system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 417system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 418system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 419system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 420system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 421system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 422system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution --- 52 unchanged lines hidden --- |