| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated |
| 4sim_ticks 41368500 # Number of ticks simulated 5final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 41370500 # Number of ticks simulated 5final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 372083 # Simulator instruction rate (inst/s) 8host_op_rate 371955 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1014555487 # Simulator tick rate (ticks/s) 10host_mem_usage 290028 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host | 7host_inst_rate 454115 # Simulator instruction rate (inst/s) 8host_op_rate 453939 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1238118753 # Simulator tick rate (ticks/s) 10host_mem_usage 292408 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory | 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s) |
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 18 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.workload.num_syscalls 18 # Number of system calls |
| 34system.cpu.numCycles 82737 # number of cpu cycles simulated | 34system.cpu.numCycles 82741 # number of cpu cycles simulated |
| 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 15162 # Number of instructions committed 38system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 41system.cpu.num_func_calls 385 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls 43system.cpu.num_int_insts 12219 # number of integer instructions 44system.cpu.num_fp_insts 0 # number of float instructions 45system.cpu.num_int_register_reads 29037 # number of times the integer registers were read 46system.cpu.num_int_register_writes 13818 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 49system.cpu.num_mem_refs 3683 # number of memory refs 50system.cpu.num_load_insts 2231 # Number of load instructions 51system.cpu.num_store_insts 1452 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37system.cpu.committedInsts 15162 # Number of instructions committed 38system.cpu.committedOps 15162 # Number of ops (including micro ops) committed 39system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses 40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 41system.cpu.num_func_calls 385 # number of times a function call or return occured 42system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls 43system.cpu.num_int_insts 12219 # number of integer instructions 44system.cpu.num_fp_insts 0 # number of float instructions 45system.cpu.num_int_register_reads 29037 # number of times the integer registers were read 46system.cpu.num_int_register_writes 13818 # number of times the integer registers were written 47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 49system.cpu.num_mem_refs 3683 # number of memory refs 50system.cpu.num_load_insts 2231 # Number of load instructions 51system.cpu.num_store_insts 1452 # Number of store instructions 52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 53system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles | 53system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles |
| 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 3363 # Number of branches fetched 57system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction 58system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction 61system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction 87system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction 88system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 15207 # Class of executed instruction 92system.cpu.dcache.tags.replacements 0 # number of replacements | 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 56system.cpu.Branches 3363 # Number of branches fetched 57system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction 58system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction 59system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction 60system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction 61system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction 86system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction 87system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction 88system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction 89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 91system.cpu.op_class::total 15207 # Class of executed instruction 92system.cpu.dcache.tags.replacements 0 # number of replacements |
| 93system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use | 93system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use |
| 94system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 94system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. 95system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 96system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. 97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 98system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor | 98system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor |
| 99system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 104system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 105system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 106system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses --- 86 unchanged lines hidden (view full) --- 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 196system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 198system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 199system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 200system.cpu.icache.tags.replacements 0 # number of replacements | 99system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy 100system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy 101system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 102system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 103system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 104system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id 105system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses 106system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses --- 86 unchanged lines hidden (view full) --- 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 196system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 198system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 199system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 200system.cpu.icache.tags.replacements 0 # number of replacements |
| 201system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use | 201system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use |
| 202system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 203system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 204system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 205system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 202system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. 203system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. 204system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. 205system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 206system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor | 206system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor |
| 207system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy 208system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 212system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 213system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 214system.cpu.icache.tags.data_accesses 30696 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 219system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 220system.cpu.icache.overall_hits::total 14928 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses 223system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 224system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses 225system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses 226system.cpu.icache.overall_misses::total 280 # number of overall misses | 207system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy 208system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 212system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id 213system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses 214system.cpu.icache.tags.data_accesses 30696 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 219system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits 220system.cpu.icache.overall_hits::total 14928 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses 223system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 224system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses 225system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses 226system.cpu.icache.overall_misses::total 280 # number of overall misses |
| 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles 228system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles 229system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles 231system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles 232system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles | 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles 228system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles 229system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles 231system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles 232system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles |
| 233system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses 236system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses 237system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses 238system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses 239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses 240system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses 241system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses 242system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses 243system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses 244system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses | 233system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses 236system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses 237system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses 238system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses 239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses 240system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses 241system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses 242system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses 243system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses 244system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses |
| 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency 246system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency 247system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency 248system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency | 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency 246system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency 247system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency 248system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency |
| 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257system.cpu.icache.fast_writes 0 # number of fast writes performed 258system.cpu.icache.cache_copies 0 # number of cache copies performed 259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 260system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 261system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 262system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 263system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 264system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses | 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257system.cpu.icache.fast_writes 0 # number of fast writes performed 258system.cpu.icache.cache_copies 0 # number of cache copies performed 259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 260system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 261system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 262system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 263system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 264system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses |
| 265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles 267system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles 268system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles 269system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles 270system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles | 265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles 267system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles 268system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles 269system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles 270system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles |
| 271system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses 273system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses 274system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses 275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 276system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses | 271system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses 273system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses 274system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses 275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses 276system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses |
| 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency 278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency 280system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency 282system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency | 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency 278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency 280system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency 282system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency |
| 283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.cpu.l2cache.tags.replacements 0 # number of replacements | 283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 285system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use | 285system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use |
| 286system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 287system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 288system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 289system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 286system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 287system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. 288system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. 289system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 290system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor 291system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor | 290system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor 291system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor |
| 292system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 297system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 298system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 299system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency 423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 292system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 297system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 298system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id 299system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency 423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 424system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 424system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 426system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 427system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution 428system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution 429system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 430system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 431system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 432system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 433system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 434system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 435system.cpu.toL2Bus.snoops 0 # Total snoops (count) 436system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram | 430system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution 435system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.snoops 0 # Total snoops (count) 442system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram |
| 437system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 438system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 443system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram 444system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram |
| 439system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 445system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 440system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 441system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram | 446system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram 447system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram |
| 442system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 443system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 448system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 449system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 444system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 450system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 445system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 446system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 447system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 448system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 449system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 450system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 451system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 452system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) --- 25 unchanged lines hidden --- | 451system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 453system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 454system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 455system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 456system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 458system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) --- 25 unchanged lines hidden --- |