| stats.txt (10220:9eab5efc02e8) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated 4sim_ticks 41368000 # Number of ticks simulated 5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated 4sim_ticks 41368000 # Number of ticks simulated 5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 324057 # Simulator instruction rate (inst/s) 8host_op_rate 323947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 883591781 # Simulator tick rate (ticks/s) 10host_mem_usage 269720 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 245276 # Simulator instruction rate (inst/s) 8host_op_rate 245221 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 668919684 # Simulator tick rate (ticks/s) 10host_mem_usage 285672 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host |
| 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 15162 # Number of instructions simulated 13sim_ops 15162 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 4 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) |
| 32system.membus.throughput 643589248 # Throughput (bytes/s) | |
| 33system.membus.trans_dist::ReadReq 331 # Transaction distribution 34system.membus.trans_dist::ReadResp 331 # Transaction distribution 35system.membus.trans_dist::ReadExReq 85 # Transaction distribution 36system.membus.trans_dist::ReadExResp 85 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) | 32system.membus.trans_dist::ReadReq 331 # Transaction distribution 33system.membus.trans_dist::ReadResp 331 # Transaction distribution 34system.membus.trans_dist::ReadExReq 85 # Transaction distribution 35system.membus.trans_dist::ReadExResp 85 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) |
| 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 26624 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 416 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 416 # Request fanout histogram |
| 43system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 45system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.workload.num_syscalls 18 # Number of system calls 49system.cpu.numCycles 82736 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started --- 371 unchanged lines hidden (view full) --- 422system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 423system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 424system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 425system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 426system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 427system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 428system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 429system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 51system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.workload.num_syscalls 18 # Number of system calls 57system.cpu.numCycles 82736 # number of cpu cycles simulated 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started --- 371 unchanged lines hidden (view full) --- 430system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 431system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 432system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 433system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 434system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 435system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 436system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 437system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 430system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s) | |
| 431system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 435system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) | 438system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution 442system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) |
| 438system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) 442system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.snoops 0 # Total snoops (count) 449system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram |
| 443system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 444system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 445system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 446system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 447system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 448system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 449 450---------- End Simulation Statistics ---------- | 460system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 461system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 462system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) 463system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 464system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 465system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 466 467---------- End Simulation Statistics ---------- |