7,11c7,11
< host_inst_rate 130693 # Simulator instruction rate (inst/s)
< host_op_rate 130661 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 359830859 # Simulator tick rate (ticks/s)
< host_mem_usage 220580 # Number of bytes of host memory used
< host_seconds 0.12 # Real time elapsed on the host
---
> host_inst_rate 488993 # Simulator instruction rate (inst/s)
> host_op_rate 488707 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1345414902 # Simulator tick rate (ticks/s)
> host_mem_usage 221064 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 26624 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 416 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s)
79a87
> system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses
80a89
> system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses
81a91
> system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses
82a93
> system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency
83a95
> system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency
84a97
> system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency
105a119
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses
106a121
> system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses
107a123
> system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses
108a125
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
109a127
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
110a129
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
157a177
> system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses
158a179
> system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
159a181
> system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses
160a183
> system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses
161a185
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
162a187
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
163a189
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
164a191
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
189a217
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses
190a219
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
191a221
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses
192a223
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses
193a225
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
194a227
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
195a229
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
196a231
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
249a285
> system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
250a287
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
252a290
> system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
254a293
> system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
256a296
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
257a298
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
259a301
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
261a304
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
293a337
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
294a339
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
296a342
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
298a345
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
300a348
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
301a350
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
303a353
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
305a356
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< host_inst_rate 130693 # Simulator instruction rate (inst/s)
< host_op_rate 130661 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 359830859 # Simulator tick rate (ticks/s)
< host_mem_usage 220580 # Number of bytes of host memory used
< host_seconds 0.12 # Real time elapsed on the host
---
> host_inst_rate 488993 # Simulator instruction rate (inst/s)
> host_op_rate 488707 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1345414902 # Simulator tick rate (ticks/s)
> host_mem_usage 221064 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 26624 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 416 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s)
79a87
> system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses
80a89
> system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses
81a91
> system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses
82a93
> system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency
83a95
> system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency
84a97
> system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency
105a119
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses
106a121
> system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses
107a123
> system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses
108a125
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
109a127
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
110a129
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
157a177
> system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses
158a179
> system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
159a181
> system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses
160a183
> system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses
161a185
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
162a187
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
163a189
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
164a191
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
189a217
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses
190a219
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
191a221
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses
192a223
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses
193a225
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
194a227
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
195a229
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
196a231
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
249a285
> system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
250a287
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
252a290
> system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
254a293
> system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
256a296
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
257a298
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
259a301
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
261a304
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
293a337
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
294a339
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
296a342
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
298a345
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
300a348
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
301a350
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
303a353
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
305a356
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency