3,5c3,5
< sim_seconds 0.000044 # Number of seconds simulated
< sim_ticks 44282500 # Number of ticks simulated
< final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000045 # Number of seconds simulated
> sim_ticks 44698500 # Number of ticks simulated
> final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 322672 # Simulator instruction rate (inst/s)
< host_op_rate 322568 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 941828647 # Simulator tick rate (ticks/s)
< host_mem_usage 247000 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 128576 # Simulator instruction rate (inst/s)
> host_op_rate 128568 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 379003891 # Simulator tick rate (ticks/s)
> host_mem_usage 250608 # Number of bytes of host memory used
> host_seconds 0.12 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 88565 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 89397 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy
111c111
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
130,137c130,137
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles
156,163c156,163
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
178,185c178,185
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles
194,202c194,202
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
204c204
< system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use
209,211c209,211
< system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy
218c218
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
231,236c231,236
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles
249,254c249,254
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency
267,272c267,272
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles
279,285c279,285
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
287c287
< system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use
289,290c289,290
< system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks.
292,297c292,297
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
299,300c299,300
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id
303c303
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
322,333c322,333
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles
358,369c358,369
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency
388,399c388,399
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles
412,423c412,423
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
430c430
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
461c461,467
< system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.000044 # Number of seconds simulated
< sim_ticks 44282500 # Number of ticks simulated
< final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000045 # Number of seconds simulated
> sim_ticks 44698500 # Number of ticks simulated
> final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 322672 # Simulator instruction rate (inst/s)
< host_op_rate 322568 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 941828647 # Simulator tick rate (ticks/s)
< host_mem_usage 247000 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 128576 # Simulator instruction rate (inst/s)
> host_op_rate 128568 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 379003891 # Simulator tick rate (ticks/s)
> host_mem_usage 250608 # Number of bytes of host memory used
> host_seconds 0.12 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
36,37c36,37
< system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 88565 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 89397 # number of cpu cycles simulated
56c56
< system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles
95c95
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
97c97
< system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use
102,104c102,104
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy
111c111
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
130,137c130,137
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles
156,163c156,163
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
178,185c178,185
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles
194,202c194,202
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
204c204
< system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use
209,211c209,211
< system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy
218c218
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
231,236c231,236
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles
249,254c249,254
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency
267,272c267,272
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles
279,285c279,285
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
287c287
< system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use
289,290c289,290
< system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks.
292,297c292,297
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
299,300c299,300
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id
303c303
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
322,333c322,333
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles
358,369c358,369
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency
388,399c388,399
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles
412,423c412,423
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency
430c430
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states
461c461,467
< system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states