4,5c4,5
< sim_ticks 41368500 # Number of ticks simulated
< final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 41370500 # Number of ticks simulated
> final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 372083 # Simulator instruction rate (inst/s)
< host_op_rate 371955 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1014555487 # Simulator tick rate (ticks/s)
< host_mem_usage 290028 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 454115 # Simulator instruction rate (inst/s)
> host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
> host_mem_usage 292408 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
34c34
< system.cpu.numCycles 82737 # number of cpu cycles simulated
---
> system.cpu.numCycles 82741 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
98c98
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
201c201
< system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
206c206
< system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
227,232c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
245,250c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
265,270c265,270
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
277,282c277,282
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
285c285
< system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
290,291c290,291
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
423a424,429
> system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
437,438c443,444
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
440,441c446,447
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
444c450
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 41368500 # Number of ticks simulated
< final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 41370500 # Number of ticks simulated
> final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 372083 # Simulator instruction rate (inst/s)
< host_op_rate 371955 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1014555487 # Simulator tick rate (ticks/s)
< host_mem_usage 290028 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 454115 # Simulator instruction rate (inst/s)
> host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
> host_mem_usage 292408 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
34c34
< system.cpu.numCycles 82737 # number of cpu cycles simulated
---
> system.cpu.numCycles 82741 # number of cpu cycles simulated
53c53
< system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
93c93
< system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
98c98
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
201c201
< system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
206c206
< system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
227,232c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
245,250c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
265,270c265,270
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
277,282c277,282
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
285c285
< system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
290,291c290,291
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
423a424,429
> system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
437,438c443,444
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
440,441c446,447
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
444c450
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram