4,5c4,5
< sim_ticks 41368000 # Number of ticks simulated
< final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 41368500 # Number of ticks simulated
> final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 245276 # Simulator instruction rate (inst/s)
< host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 668919684 # Simulator tick rate (ticks/s)
< host_mem_usage 285672 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 311873 # Simulator instruction rate (inst/s)
> host_op_rate 311783 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 850451247 # Simulator tick rate (ticks/s)
> host_mem_usage 289340 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
24,54c24,31
< system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 331 # Transaction distribution
< system.membus.trans_dist::ReadResp 331 # Transaction distribution
< system.membus.trans_dist::ReadExReq 85 # Transaction distribution
< system.membus.trans_dist::ReadExResp 85 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 416 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 416 # Request fanout histogram
< system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
57c34
< system.cpu.numCycles 82736 # number of cpu cycles simulated
---
> system.cpu.numCycles 82737 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
114a92,199
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
> system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
> system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
> system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
> system.cpu.dcache.overall_hits::total 3529 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
> system.cpu.dcache.overall_misses::total 138 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c201
< system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use
121,123c206,208
< system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy
142,147c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
160,165c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
180,185c265,270
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles
192,197c277,282
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency
200c285
< system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use
205,207c290,292
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
209c294
< system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
233,243c318,328
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
266,276c351,361
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency
296,306c381,391
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles
318,328c403,413
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
330,437d414
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
< system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
< system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
< system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
< system.cpu.dcache.overall_hits::total 3529 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
< system.cpu.dcache.overall_misses::total 138 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
465a443,465
> system.membus.trans_dist::ReadReq 331 # Transaction distribution
> system.membus.trans_dist::ReadResp 331 # Transaction distribution
> system.membus.trans_dist::ReadExReq 85 # Transaction distribution
> system.membus.trans_dist::ReadExResp 85 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 416 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 416 # Request fanout histogram
> system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
< sim_ticks 41368000 # Number of ticks simulated
< final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 41368500 # Number of ticks simulated
> final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 245276 # Simulator instruction rate (inst/s)
< host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 668919684 # Simulator tick rate (ticks/s)
< host_mem_usage 285672 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 311873 # Simulator instruction rate (inst/s)
> host_op_rate 311783 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 850451247 # Simulator tick rate (ticks/s)
> host_mem_usage 289340 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
24,54c24,31
< system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 331 # Transaction distribution
< system.membus.trans_dist::ReadResp 331 # Transaction distribution
< system.membus.trans_dist::ReadExReq 85 # Transaction distribution
< system.membus.trans_dist::ReadExResp 85 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 416 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 416 # Request fanout histogram
< system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
57c34
< system.cpu.numCycles 82736 # number of cpu cycles simulated
---
> system.cpu.numCycles 82737 # number of cpu cycles simulated
76c53
< system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
114a92,199
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
> system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
> system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
> system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
> system.cpu.dcache.overall_hits::total 3529 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
> system.cpu.dcache.overall_misses::total 138 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
116c201
< system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use
121,123c206,208
< system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy
142,147c227,232
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
160,165c245,250
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
180,185c265,270
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles
192,197c277,282
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency
200c285
< system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use
205,207c290,292
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
209c294
< system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
233,243c318,328
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
266,276c351,361
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency
296,306c381,391
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles
318,328c403,413
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
330,437d414
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
< system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
< system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
< system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
< system.cpu.dcache.overall_hits::total 3529 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
< system.cpu.dcache.overall_misses::total 138 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
465a443,465
> system.membus.trans_dist::ReadReq 331 # Transaction distribution
> system.membus.trans_dist::ReadResp 331 # Transaction distribution
> system.membus.trans_dist::ReadExReq 85 # Transaction distribution
> system.membus.trans_dist::ReadExResp 85 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 416 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 416 # Request fanout histogram
> system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 5.0 # Layer utilization (%)