1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
4sim_ticks 41368000 # Number of ticks simulated
5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
4sim_ticks 41368000 # Number of ticks simulated
5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 26295 # Simulator instruction rate (inst/s)
8host_op_rate 26295 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 71739884 # Simulator tick rate (ticks/s)
10host_mem_usage 277420 # Number of bytes of host memory used
11host_seconds 0.58 # Real time elapsed on the host
| 7host_inst_rate 479032 # Simulator instruction rate (inst/s)
8host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
10host_mem_usage 231320 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
|
12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
16system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
| 12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
16system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
|
| 30system.membus.throughput 643589248 # Throughput (bytes/s)
31system.membus.trans_dist::ReadReq 331 # Transaction distribution
32system.membus.trans_dist::ReadResp 331 # Transaction distribution
33system.membus.trans_dist::ReadExReq 85 # Transaction distribution
34system.membus.trans_dist::ReadExResp 85 # Transaction distribution
35system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
36system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
38system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
39system.membus.data_through_bus 26624 # Total data (bytes)
40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
42system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
43system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
44system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
|
30system.cpu.workload.num_syscalls 18 # Number of system calls
31system.cpu.numCycles 82736 # number of cpu cycles simulated
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34system.cpu.committedInsts 15162 # Number of instructions committed
35system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
36system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
38system.cpu.num_func_calls 385 # number of times a function call or return occured
39system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
40system.cpu.num_int_insts 12219 # number of integer instructions
41system.cpu.num_fp_insts 0 # number of float instructions
42system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
43system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
46system.cpu.num_mem_refs 3683 # number of memory refs
47system.cpu.num_load_insts 2231 # Number of load instructions
48system.cpu.num_store_insts 1452 # Number of store instructions
49system.cpu.num_idle_cycles 0 # Number of idle cycles
50system.cpu.num_busy_cycles 82736 # Number of busy cycles
51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
52system.cpu.idle_fraction 0 # Percentage of idle cycles
53system.cpu.icache.replacements 0 # number of replacements
54system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use
55system.cpu.icache.total_refs 14928 # Total number of references to valid blocks.
56system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
57system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks.
58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
60system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
61system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy
62system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
63system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
64system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
65system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
66system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
67system.cpu.icache.overall_hits::total 14928 # number of overall hits
68system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
69system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
70system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
71system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
72system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
73system.cpu.icache.overall_misses::total 280 # number of overall misses
74system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
75system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
76system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
77system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
78system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
79system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
80system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
81system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
82system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
83system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
84system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
85system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
87system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
88system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
89system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
90system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
91system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
93system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
94system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
95system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
96system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
97system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
104system.cpu.icache.fast_writes 0 # number of fast writes performed
105system.cpu.icache.cache_copies 0 # number of cache copies performed
106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
107system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
108system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
109system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
110system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
111system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
113system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
115system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
117system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
121system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
123system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
127system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
129system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131system.cpu.l2cache.replacements 0 # number of replacements
132system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
133system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
134system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
135system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
136system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
137system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
138system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
139system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
140system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
141system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy
142system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
143system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
144system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
145system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
146system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
147system.cpu.l2cache.overall_hits::total 2 # number of overall hits
148system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
149system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
150system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
151system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
152system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
153system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
154system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
155system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
156system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
157system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
158system.cpu.l2cache.overall_misses::total 416 # number of overall misses
159system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
160system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
161system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
162system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
163system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
164system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
165system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
166system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
167system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
168system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
169system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
170system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
171system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
172system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
173system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
174system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
175system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
176system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
177system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
178system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
179system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
180system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
181system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
182system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
183system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
184system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
185system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
186system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
187system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
188system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
189system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
190system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
191system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
192system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
193system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
194system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
195system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
196system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
197system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
198system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
199system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
200system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
201system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
202system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
203system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
204system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
205system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
206system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
207system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
208system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
209system.cpu.l2cache.fast_writes 0 # number of fast writes performed
210system.cpu.l2cache.cache_copies 0 # number of cache copies performed
211system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
212system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
213system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
214system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
215system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
216system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
217system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
218system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
219system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
220system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
221system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
222system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
223system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
224system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
225system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
226system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
227system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
228system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
229system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
230system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
231system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
232system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
233system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
234system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
235system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
236system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
237system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
238system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
239system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
240system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
241system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
242system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
243system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
244system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
245system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
246system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
247system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
248system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
249system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
250system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
251system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
252system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
253system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
254system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
255system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
256system.cpu.dcache.replacements 0 # number of replacements
257system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
258system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
259system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
260system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
261system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
262system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
263system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
264system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
265system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
266system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
267system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
268system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
269system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
270system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
271system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
272system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
273system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
274system.cpu.dcache.overall_hits::total 3529 # number of overall hits
275system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
276system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
277system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
278system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
279system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
280system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
281system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
282system.cpu.dcache.overall_misses::total 138 # number of overall misses
283system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
284system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
285system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
286system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
287system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
288system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
289system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
290system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
291system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
292system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
293system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
294system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
295system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
296system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
297system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
298system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
299system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
300system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
301system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
302system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
303system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
304system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
305system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
306system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
307system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
308system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
309system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
310system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
311system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
312system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
313system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
314system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
315system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
316system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
317system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
318system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
319system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
320system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
321system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
322system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
323system.cpu.dcache.fast_writes 0 # number of fast writes performed
324system.cpu.dcache.cache_copies 0 # number of cache copies performed
325system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
326system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
327system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
328system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
329system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
330system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
331system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
332system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
333system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
334system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
335system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
336system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
337system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
338system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
339system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
340system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
341system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
342system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
343system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
344system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
345system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
346system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
347system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
348system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
349system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
350system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
351system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
353system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
354system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
355system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
356system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
357system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 45system.cpu.workload.num_syscalls 18 # Number of system calls
46system.cpu.numCycles 82736 # number of cpu cycles simulated
47system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
48system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
49system.cpu.committedInsts 15162 # Number of instructions committed
50system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
51system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
52system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
53system.cpu.num_func_calls 385 # number of times a function call or return occured
54system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
55system.cpu.num_int_insts 12219 # number of integer instructions
56system.cpu.num_fp_insts 0 # number of float instructions
57system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
58system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
59system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
60system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
61system.cpu.num_mem_refs 3683 # number of memory refs
62system.cpu.num_load_insts 2231 # Number of load instructions
63system.cpu.num_store_insts 1452 # Number of store instructions
64system.cpu.num_idle_cycles 0 # Number of idle cycles
65system.cpu.num_busy_cycles 82736 # Number of busy cycles
66system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
67system.cpu.idle_fraction 0 # Percentage of idle cycles
68system.cpu.icache.replacements 0 # number of replacements
69system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use
70system.cpu.icache.total_refs 14928 # Total number of references to valid blocks.
71system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
72system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks.
73system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
74system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
75system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
76system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy
77system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
78system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
79system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
80system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
81system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
82system.cpu.icache.overall_hits::total 14928 # number of overall hits
83system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
84system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
85system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
86system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
87system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
88system.cpu.icache.overall_misses::total 280 # number of overall misses
89system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
90system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
91system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
92system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
93system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
94system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
95system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
96system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
97system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
98system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
99system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
100system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
101system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
102system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
103system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
104system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
105system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
106system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
107system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
108system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
109system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
110system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
111system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
112system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
113system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
114system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
115system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
116system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
117system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
118system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
119system.cpu.icache.fast_writes 0 # number of fast writes performed
120system.cpu.icache.cache_copies 0 # number of cache copies performed
121system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
122system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
123system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
124system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
125system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
126system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
127system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
128system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
129system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
130system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
131system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
132system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
133system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
134system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
135system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
136system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
137system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
138system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
139system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
140system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
141system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
142system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
143system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
144system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
145system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
146system.cpu.l2cache.replacements 0 # number of replacements
147system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
148system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
149system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
150system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
151system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
152system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
153system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
154system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
155system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
156system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy
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158system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
159system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
160system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
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162system.cpu.l2cache.overall_hits::total 2 # number of overall hits
163system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
164system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
165system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
166system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
167system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
168system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
169system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
170system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
171system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
172system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
173system.cpu.l2cache.overall_misses::total 416 # number of overall misses
174system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
175system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
176system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
177system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
178system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
179system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
180system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
181system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
182system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
183system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
184system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
185system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
186system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
187system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
188system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
189system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
190system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
191system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
192system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
193system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
194system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
195system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
196system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
197system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
198system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses
199system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
200system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
201system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
202system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
203system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
204system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
205system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
206system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
207system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
208system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
209system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
210system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
211system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
212system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
213system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
214system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
215system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
216system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
217system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
218system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
219system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
220system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
221system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
222system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
223system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
224system.cpu.l2cache.fast_writes 0 # number of fast writes performed
225system.cpu.l2cache.cache_copies 0 # number of cache copies performed
226system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
227system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
228system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
229system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
230system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
231system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
232system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
233system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
234system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
235system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
236system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
237system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
238system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
239system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
240system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
241system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
242system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
243system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
244system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
245system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
246system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
247system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
248system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
249system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
250system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
251system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
252system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
253system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
254system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
255system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
256system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
257system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
258system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
261system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
262system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
263system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
264system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
265system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
266system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
267system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
268system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
269system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
270system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
271system.cpu.dcache.replacements 0 # number of replacements
272system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
273system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
274system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
275system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
276system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
277system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
278system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
279system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
280system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
281system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
282system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
283system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
284system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
285system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
286system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
287system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
288system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
289system.cpu.dcache.overall_hits::total 3529 # number of overall hits
290system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
291system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
292system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
293system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
294system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
295system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
296system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
297system.cpu.dcache.overall_misses::total 138 # number of overall misses
298system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
299system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
300system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
301system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
302system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
303system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
304system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
305system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
306system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
307system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
308system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
309system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
310system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
311system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
312system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
313system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
314system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
315system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
316system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
317system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
318system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
319system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
320system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
321system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
322system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
323system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
324system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
325system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
326system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
327system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
328system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
329system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
330system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
331system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
332system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
333system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
334system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
335system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
336system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
337system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
338system.cpu.dcache.fast_writes 0 # number of fast writes performed
339system.cpu.dcache.cache_copies 0 # number of cache copies performed
340system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
341system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
342system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
343system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
344system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
345system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
346system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
347system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
348system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
349system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
350system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
351system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
352system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
353system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
354system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
355system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
356system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
357system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
358system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
359system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
360system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
361system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
362system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
363system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
364system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
365system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
366system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
367system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
368system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
369system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
370system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
371system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 373system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
374system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
375system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
376system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
377system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
378system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
379system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
380system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
381system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
382system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
383system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
384system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
385system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
386system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
387system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
388system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
389system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
390system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
391system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
358
359---------- End Simulation Statistics ----------
| 392
393---------- End Simulation Statistics ----------
|