1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
|
4sim_ticks 41368500 # Number of ticks simulated
5final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 4sim_ticks 41370500 # Number of ticks simulated
5final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 372083 # Simulator instruction rate (inst/s)
8host_op_rate 371955 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1014555487 # Simulator tick rate (ticks/s)
10host_mem_usage 290028 # Number of bytes of host memory used
11host_seconds 0.04 # Real time elapsed on the host
| 7host_inst_rate 454115 # Simulator instruction rate (inst/s)
8host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
10host_mem_usage 292408 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
|
12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
| 12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
|
24system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
| 24system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
|
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 18 # Number of system calls
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.workload.num_syscalls 18 # Number of system calls
|
34system.cpu.numCycles 82737 # number of cpu cycles simulated
| 34system.cpu.numCycles 82741 # number of cpu cycles simulated
|
35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 15162 # Number of instructions committed
38system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
41system.cpu.num_func_calls 385 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
43system.cpu.num_int_insts 12219 # number of integer instructions
44system.cpu.num_fp_insts 0 # number of float instructions
45system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
46system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
49system.cpu.num_mem_refs 3683 # number of memory refs
50system.cpu.num_load_insts 2231 # Number of load instructions
51system.cpu.num_store_insts 1452 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
| 35system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
36system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
37system.cpu.committedInsts 15162 # Number of instructions committed
38system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
39system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
40system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
41system.cpu.num_func_calls 385 # number of times a function call or return occured
42system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
43system.cpu.num_int_insts 12219 # number of integer instructions
44system.cpu.num_fp_insts 0 # number of float instructions
45system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
46system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
47system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
48system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
49system.cpu.num_mem_refs 3683 # number of memory refs
50system.cpu.num_load_insts 2231 # Number of load instructions
51system.cpu.num_store_insts 1452 # Number of store instructions
52system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
53system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
| 53system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
|
54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 3363 # Number of branches fetched
57system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
58system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
61system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
62system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
63system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
64system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
65system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
66system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
67system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
68system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
69system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
70system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
71system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
72system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
73system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
74system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
75system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
76system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
77system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
78system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
79system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
80system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
81system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
82system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
83system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
84system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
87system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
88system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 15207 # Class of executed instruction
92system.cpu.dcache.tags.replacements 0 # number of replacements
| 54system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
55system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
56system.cpu.Branches 3363 # Number of branches fetched
57system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
58system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
59system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
60system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
61system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
62system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction
63system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction
64system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction
65system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction
66system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction
67system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction
68system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction
69system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction
70system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction
71system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction
72system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction
73system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction
74system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction
75system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction
76system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction
77system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction
78system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction
79system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction
80system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction
81system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction
82system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction
83system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction
84system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
85system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
86system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
87system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
88system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
89system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
90system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
91system.cpu.op_class::total 15207 # Class of executed instruction
92system.cpu.dcache.tags.replacements 0 # number of replacements
|
93system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use
| 93system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
|
94system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 94system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
95system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
96system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
97system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
98system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor
| 98system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
|
99system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
104system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
105system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
106system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
107system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
108system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
109system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
110system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
111system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
112system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
113system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
114system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
115system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
116system.cpu.dcache.overall_hits::total 3529 # number of overall hits
117system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
118system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
119system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
120system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
121system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
122system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
123system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
124system.cpu.dcache.overall_misses::total 138 # number of overall misses
125system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
126system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
127system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
128system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
129system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
130system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
131system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
132system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
133system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
134system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
135system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
136system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
137system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
138system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
139system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
140system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
141system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
142system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
143system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
144system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
145system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
146system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
147system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
148system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
149system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
150system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
151system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
152system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
153system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
154system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
155system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
156system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
157system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
158system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
159system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
160system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
161system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
164system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
165system.cpu.dcache.fast_writes 0 # number of fast writes performed
166system.cpu.dcache.cache_copies 0 # number of cache copies performed
167system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
168system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
169system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
170system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
171system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
172system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
173system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
174system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
175system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles
176system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles
177system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles
178system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles
179system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles
180system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles
181system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles
182system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles
183system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
184system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
185system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
186system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
188system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
190system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
196system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
197system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
198system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
199system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
200system.cpu.icache.tags.replacements 0 # number of replacements
| 99system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy
100system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy
101system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
102system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
103system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
104system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
105system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
106system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
107system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
108system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
109system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
110system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
111system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
112system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
113system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
114system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
115system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
116system.cpu.dcache.overall_hits::total 3529 # number of overall hits
117system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
118system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
119system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
120system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
121system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
122system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
123system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
124system.cpu.dcache.overall_misses::total 138 # number of overall misses
125system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
126system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
127system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
128system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
129system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
130system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
131system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
132system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
133system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
134system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
135system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
136system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
137system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
138system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
139system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
140system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
141system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
142system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
143system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
144system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
145system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
146system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
147system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
148system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
149system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
150system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
151system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
152system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
153system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
154system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
155system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
156system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
157system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
158system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
159system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
160system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
161system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
164system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
165system.cpu.dcache.fast_writes 0 # number of fast writes performed
166system.cpu.dcache.cache_copies 0 # number of cache copies performed
167system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
168system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
169system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
170system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
171system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
172system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
173system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
174system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
175system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles
176system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles
177system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles
178system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles
179system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles
180system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles
181system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles
182system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles
183system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
184system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
185system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
186system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
188system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
189system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
190system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
196system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
197system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
198system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
199system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
200system.cpu.icache.tags.replacements 0 # number of replacements
|
201system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use
| 201system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
|
202system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
203system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
204system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
205system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 202system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
203system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
204system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
205system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
206system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor
| 206system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
|
207system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy
208system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
210system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
212system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
213system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
214system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
215system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
216system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
217system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
218system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
219system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
220system.cpu.icache.overall_hits::total 14928 # number of overall hits
221system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
222system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
223system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
224system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
225system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
226system.cpu.icache.overall_misses::total 280 # number of overall misses
| 207system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy
208system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
210system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
212system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
213system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
214system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
215system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
216system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
217system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
218system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
219system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
220system.cpu.icache.overall_hits::total 14928 # number of overall hits
221system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
222system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
223system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
224system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
225system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
226system.cpu.icache.overall_misses::total 280 # number of overall misses
|
227system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
228system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
229system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
230system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
231system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
232system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
| 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
228system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
229system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
230system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
231system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
232system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
|
233system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
234system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
235system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
236system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
237system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
238system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
240system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
241system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
242system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
243system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
244system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
| 233system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
234system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
235system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
236system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
237system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
238system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
240system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
241system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
242system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
243system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
244system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
|
245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
246system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
247system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
248system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
249system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
250system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
| 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
246system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
247system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
248system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
249system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
250system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
|
251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
257system.cpu.icache.fast_writes 0 # number of fast writes performed
258system.cpu.icache.cache_copies 0 # number of cache copies performed
259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
260system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
261system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
262system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
263system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
264system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
| 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
257system.cpu.icache.fast_writes 0 # number of fast writes performed
258system.cpu.icache.cache_copies 0 # number of cache copies performed
259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
260system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
261system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
262system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
263system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
264system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
|
265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles
266system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles
267system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles
268system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles
269system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles
270system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles
| 265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
266system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
267system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
268system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
269system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
270system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
|
271system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
272system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
273system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
274system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
276system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
| 271system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
272system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
273system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
274system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
276system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
|
277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency
278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency
279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
280system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
282system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
| 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
280system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
282system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
284system.cpu.l2cache.tags.replacements 0 # number of replacements
| 283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
284system.cpu.l2cache.tags.replacements 0 # number of replacements
|
285system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use
| 285system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
|
286system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
287system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
288system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
289system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 286system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
287system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
288system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
289system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
290system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor
291system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor
| 290system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
291system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
|
292system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
293system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
294system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
295system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
296system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
297system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
298system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
299system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
300system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
301system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
302system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
303system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
304system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
305system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
306system.cpu.l2cache.overall_hits::total 2 # number of overall hits
307system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
308system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
309system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
310system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
311system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
312system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
313system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
314system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
315system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
316system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
317system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
318system.cpu.l2cache.overall_misses::total 416 # number of overall misses
319system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
320system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
321system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
322system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
323system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
324system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
325system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
326system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles
327system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
328system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
329system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles
330system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
331system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
332system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
333system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
334system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses)
335system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses)
336system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses)
337system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
338system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
339system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
340system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
341system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
342system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
343system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
344system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
345system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses
346system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses
347system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
348system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
349system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
350system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
351system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
352system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
353system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
354system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
355system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
356system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
357system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
358system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
359system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
360system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
361system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
362system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
363system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency
364system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
365system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
366system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency
367system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
368system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
369system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
370system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
373system.cpu.l2cache.fast_writes 0 # number of fast writes performed
374system.cpu.l2cache.cache_copies 0 # number of cache copies performed
375system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
376system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
377system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
378system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
379system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses
380system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses
381system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
382system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
383system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
384system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
385system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
386system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
387system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles
388system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles
389system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
391system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
393system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
394system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles
395system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
396system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
397system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles
398system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
399system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
400system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
401system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses
403system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
405system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
406system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
407system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
408system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
409system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
410system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
411system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
413system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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293system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
294system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
295system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
296system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
297system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
298system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
299system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
300system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
301system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
302system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
303system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
304system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
305system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
306system.cpu.l2cache.overall_hits::total 2 # number of overall hits
307system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
308system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
309system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
310system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
311system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses
312system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses
313system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
314system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
315system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
316system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
317system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
318system.cpu.l2cache.overall_misses::total 416 # number of overall misses
319system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
320system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
321system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
322system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
323system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
324system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
325system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
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327system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
328system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
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330system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
331system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
332system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
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334system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses)
335system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses)
336system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses)
337system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
338system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
339system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
340system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
341system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
342system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
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344system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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346system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses
347system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
348system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
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355system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
356system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
357system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
358system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
359system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
360system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
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364system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
365system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
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370system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
373system.cpu.l2cache.fast_writes 0 # number of fast writes performed
374system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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382system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
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385system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
386system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
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388system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles
389system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
390system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
391system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
392system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
393system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
394system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles
395system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
396system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
397system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles
398system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
399system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
400system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
401system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses
403system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
405system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
406system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
407system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
408system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
409system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
410system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
411system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
412system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
413system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
414system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
416system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
418system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
419system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
421system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
422system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
423system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 424system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
425system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
426system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
427system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
428system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
429system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
424system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
425system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
426system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
427system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution
428system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution
429system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
430system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
431system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
432system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
433system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
434system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
435system.cpu.toL2Bus.snoops 0 # Total snoops (count)
436system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
| 430system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
431system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
432system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
433system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution
434system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution
435system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
436system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
437system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
438system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
439system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
440system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
441system.cpu.toL2Bus.snoops 0 # Total snoops (count)
442system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
|
437system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
438system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
| 443system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
444system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
|
439system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
| 445system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
440system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
441system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
| 446system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
447system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
|
442system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
443system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
| 448system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
449system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
444system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
| 450system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
445system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
446system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
447system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
448system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
449system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
450system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
451system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
452system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
453system.membus.trans_dist::ReadResp 331 # Transaction distribution
454system.membus.trans_dist::ReadExReq 85 # Transaction distribution
455system.membus.trans_dist::ReadExResp 85 # Transaction distribution
456system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution
457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
458system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
459system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
460system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
461system.membus.snoops 0 # Total snoops (count)
462system.membus.snoop_fanout::samples 416 # Request fanout histogram
463system.membus.snoop_fanout::mean 0 # Request fanout histogram
464system.membus.snoop_fanout::stdev 0 # Request fanout histogram
465system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
466system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
467system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
468system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
469system.membus.snoop_fanout::min_value 0 # Request fanout histogram
470system.membus.snoop_fanout::max_value 0 # Request fanout histogram
471system.membus.snoop_fanout::total 416 # Request fanout histogram
472system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
473system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
474system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
475system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
476
477---------- End Simulation Statistics ----------
| 451system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
452system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
453system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
454system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
455system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
456system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
457system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
458system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
459system.membus.trans_dist::ReadResp 331 # Transaction distribution
460system.membus.trans_dist::ReadExReq 85 # Transaction distribution
461system.membus.trans_dist::ReadExResp 85 # Transaction distribution
462system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution
463system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
464system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
465system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
466system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
467system.membus.snoops 0 # Total snoops (count)
468system.membus.snoop_fanout::samples 416 # Request fanout histogram
469system.membus.snoop_fanout::mean 0 # Request fanout histogram
470system.membus.snoop_fanout::stdev 0 # Request fanout histogram
471system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
472system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
473system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
474system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
475system.membus.snoop_fanout::min_value 0 # Request fanout histogram
476system.membus.snoop_fanout::max_value 0 # Request fanout histogram
477system.membus.snoop_fanout::total 416 # Request fanout histogram
478system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
479system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
480system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
481system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
482
483---------- End Simulation Statistics ----------
|