1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000042 # Number of seconds simulated
4sim_ticks 41800000 # Number of ticks simulated
5final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 130693 # Simulator instruction rate (inst/s)
8host_op_rate 130661 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 359830859 # Simulator tick rate (ticks/s)
10host_mem_usage 220580 # Number of bytes of host memory used
11host_seconds 0.12 # Real time elapsed on the host
12sim_insts 15175 # Number of instructions simulated
13sim_ops 15175 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 26624 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 416 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.workload.num_syscalls 18 # Number of system calls
24system.cpu.numCycles 83600 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.committedInsts 15175 # Number of instructions committed
28system.cpu.committedOps 15175 # Number of ops (including micro ops) committed
29system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
30system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses

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72system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles
73system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses)
74system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses
76system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses
77system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses
78system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses
79system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses
80system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses
81system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses
82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency
83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency
84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency
85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
89system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
90system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
91system.cpu.icache.fast_writes 0 # number of fast writes performed
92system.cpu.icache.cache_copies 0 # number of cache copies performed

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98system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
99system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
100system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
105system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses
106system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses
107system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses
108system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
109system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
110system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112system.cpu.dcache.replacements 0 # number of replacements
113system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use
114system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
115system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
116system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
117system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor

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150system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
151system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
152system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
153system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses
154system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses
155system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses
156system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
157system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses
158system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
159system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses
160system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses
161system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
163system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
164system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
165system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
166system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
167system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
168system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
169system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
170system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
171system.cpu.dcache.fast_writes 0 # number of fast writes performed
172system.cpu.dcache.cache_copies 0 # number of cache copies performed

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182system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
183system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
184system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
185system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
186system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
187system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
188system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
189system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
190system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
191system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
192system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
193system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
194system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
195system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
197system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
198system.cpu.l2cache.replacements 0 # number of replacements
199system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use
200system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
201system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
202system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
203system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
204system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor

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242system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
243system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
244system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
245system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
246system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
247system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
248system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
249system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
250system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
251system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
252system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
253system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
254system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
255system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
256system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
257system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
258system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
259system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
262system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
263system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
264system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
265system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
266system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
267system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
268system.cpu.l2cache.fast_writes 0 # number of fast writes performed
269system.cpu.l2cache.cache_copies 0 # number of cache copies performed

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286system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
287system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
288system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
289system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
290system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
291system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
292system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
293system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
294system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
295system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
296system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
297system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
298system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
299system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
300system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
301system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
303system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
304system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
305system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
306system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
307
308---------- End Simulation Statistics ----------