1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
4sim_ticks 41368000 # Number of ticks simulated
5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 245276 # Simulator instruction rate (inst/s)
8host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 668919684 # Simulator tick rate (ticks/s)
10host_mem_usage 285672 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host
12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
32system.membus.trans_dist::ReadReq 331 # Transaction distribution
33system.membus.trans_dist::ReadResp 331 # Transaction distribution
34system.membus.trans_dist::ReadExReq 85 # Transaction distribution
35system.membus.trans_dist::ReadExResp 85 # Transaction distribution
36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
37system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
39system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
40system.membus.snoops 0 # Total snoops (count)
41system.membus.snoop_fanout::samples 416 # Request fanout histogram
42system.membus.snoop_fanout::mean 0 # Request fanout histogram
43system.membus.snoop_fanout::stdev 0 # Request fanout histogram
44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
45system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
48system.membus.snoop_fanout::min_value 0 # Request fanout histogram
49system.membus.snoop_fanout::max_value 0 # Request fanout histogram
50system.membus.snoop_fanout::total 416 # Request fanout histogram
51system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
53system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.workload.num_syscalls 18 # Number of system calls
57system.cpu.numCycles 82736 # number of cpu cycles simulated
58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
60system.cpu.committedInsts 15162 # Number of instructions committed
61system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
62system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
63system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
64system.cpu.num_func_calls 385 # number of times a function call or return occured
65system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
66system.cpu.num_int_insts 12219 # number of integer instructions
67system.cpu.num_fp_insts 0 # number of float instructions
68system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
69system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
70system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
71system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
72system.cpu.num_mem_refs 3683 # number of memory refs
73system.cpu.num_load_insts 2231 # Number of load instructions
74system.cpu.num_store_insts 1452 # Number of store instructions
75system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
76system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles
77system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
78system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
79system.cpu.Branches 3363 # Number of branches fetched
80system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
81system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
82system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
83system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
84system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
107system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
109system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
110system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
111system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
112system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
113system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
114system.cpu.op_class::total 15207 # Class of executed instruction
115system.cpu.icache.tags.replacements 0 # number of replacements
116system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
117system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
118system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
119system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
120system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
121system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
122system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
123system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
124system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
125system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
126system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
127system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
128system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
129system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
130system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
131system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
132system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
133system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
134system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
135system.cpu.icache.overall_hits::total 14928 # number of overall hits
136system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
137system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
138system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
139system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
140system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
141system.cpu.icache.overall_misses::total 280 # number of overall misses
142system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
143system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
144system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
145system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
146system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
147system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
148system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
149system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
150system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
151system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
152system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
153system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
154system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
155system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
156system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
157system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
158system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
159system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
160system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
161system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
162system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
163system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
164system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
165system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
166system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
168system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
169system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
170system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172system.cpu.icache.fast_writes 0 # number of fast writes performed
173system.cpu.icache.cache_copies 0 # number of cache copies performed
174system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
175system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
176system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
177system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
178system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
179system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
180system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
181system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
182system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
183system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
184system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
185system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
186system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
187system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
188system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
189system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
190system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
191system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
192system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
193system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
194system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
195system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
196system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
197system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
198system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
199system.cpu.l2cache.tags.replacements 0 # number of replacements
200system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
201system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
202system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
203system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
204system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
205system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
206system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
207system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
208system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
209system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
210system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
211system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
212system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
213system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
214system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
215system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
216system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
217system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
--- 7 unchanged lines hidden (view full) ---
225system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
226system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
227system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
228system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
229system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
230system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
231system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
232system.cpu.l2cache.overall_misses::total 416 # number of overall misses
233system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
234system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
235system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
236system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
237system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
238system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
239system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
240system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
241system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
242system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
243system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
244system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
245system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
246system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
247system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
248system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
249system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
250system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
251system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
--- 6 unchanged lines hidden (view full) ---
258system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
259system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
260system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
261system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
262system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses
263system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
264system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
265system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
266system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
267system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
268system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
269system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
270system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
271system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
272system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
273system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
276system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
277system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
278system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
279system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
280system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
281system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
282system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
283system.cpu.l2cache.fast_writes 0 # number of fast writes performed
284system.cpu.l2cache.cache_copies 0 # number of cache copies performed
285system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
286system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
287system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
288system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
289system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
290system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
291system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
292system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
293system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
294system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
295system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
296system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
297system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
298system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
299system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
300system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
301system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
302system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
303system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
304system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
305system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
306system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
307system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
308system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
309system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
310system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
311system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
312system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
313system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
314system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses
315system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
316system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
317system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
318system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
319system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
320system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
321system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
322system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
323system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
324system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
325system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
326system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
327system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
328system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
329system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
330system.cpu.dcache.tags.replacements 0 # number of replacements
331system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
332system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
333system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
334system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
335system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
336system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
337system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
338system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
339system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
340system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
341system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
342system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
343system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
344system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
345system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
346system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
347system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
348system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
349system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
350system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
351system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
352system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
353system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
354system.cpu.dcache.overall_hits::total 3529 # number of overall hits
355system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
356system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
357system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
358system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
359system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
360system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
361system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
362system.cpu.dcache.overall_misses::total 138 # number of overall misses
363system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
364system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
365system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
366system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
367system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
368system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
369system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
370system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
371system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
372system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
373system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
374system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
375system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
376system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
377system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
378system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
379system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
380system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
381system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
382system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
383system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
384system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
385system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
386system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
387system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
388system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
389system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
390system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
391system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
392system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
393system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
394system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
395system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
396system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
397system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
398system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
399system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
400system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
401system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
402system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
403system.cpu.dcache.fast_writes 0 # number of fast writes performed
404system.cpu.dcache.cache_copies 0 # number of cache copies performed
405system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
406system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
407system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
408system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
409system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
410system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
411system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
412system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
413system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
414system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
415system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
416system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
417system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
418system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
419system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
420system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
421system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
422system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
423system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
424system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
425system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
426system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
427system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
428system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
429system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
430system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
431system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
432system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
433system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
434system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
435system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
436system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
437system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
439system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
440system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
441system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
442system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
443system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
444system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
--- 12 unchanged lines hidden (view full) ---
458system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
459system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
460system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
461system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
462system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
463system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
464system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
465system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
466
467---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
4sim_ticks 41368000 # Number of ticks simulated
5final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 245276 # Simulator instruction rate (inst/s)
8host_op_rate 245221 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 668919684 # Simulator tick rate (ticks/s)
10host_mem_usage 285672 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host
12sim_insts 15162 # Number of instructions simulated
13sim_ops 15162 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
32system.membus.trans_dist::ReadReq 331 # Transaction distribution
33system.membus.trans_dist::ReadResp 331 # Transaction distribution
34system.membus.trans_dist::ReadExReq 85 # Transaction distribution
35system.membus.trans_dist::ReadExResp 85 # Transaction distribution
36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
37system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
39system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
40system.membus.snoops 0 # Total snoops (count)
41system.membus.snoop_fanout::samples 416 # Request fanout histogram
42system.membus.snoop_fanout::mean 0 # Request fanout histogram
43system.membus.snoop_fanout::stdev 0 # Request fanout histogram
44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
45system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
48system.membus.snoop_fanout::min_value 0 # Request fanout histogram
49system.membus.snoop_fanout::max_value 0 # Request fanout histogram
50system.membus.snoop_fanout::total 416 # Request fanout histogram
51system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
53system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.workload.num_syscalls 18 # Number of system calls
57system.cpu.numCycles 82736 # number of cpu cycles simulated
58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
60system.cpu.committedInsts 15162 # Number of instructions committed
61system.cpu.committedOps 15162 # Number of ops (including micro ops) committed
62system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses
63system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
64system.cpu.num_func_calls 385 # number of times a function call or return occured
65system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls
66system.cpu.num_int_insts 12219 # number of integer instructions
67system.cpu.num_fp_insts 0 # number of float instructions
68system.cpu.num_int_register_reads 29037 # number of times the integer registers were read
69system.cpu.num_int_register_writes 13818 # number of times the integer registers were written
70system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
71system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
72system.cpu.num_mem_refs 3683 # number of memory refs
73system.cpu.num_load_insts 2231 # Number of load instructions
74system.cpu.num_store_insts 1452 # Number of store instructions
75system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
76system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles
77system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
78system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
79system.cpu.Branches 3363 # Number of branches fetched
80system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction
81system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction
82system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction
83system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction
84system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
107system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction
108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction
109system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction
110system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction
111system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction
112system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
113system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
114system.cpu.op_class::total 15207 # Class of executed instruction
115system.cpu.icache.tags.replacements 0 # number of replacements
116system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
117system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
118system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
119system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
120system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
121system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
122system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
123system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
124system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
125system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
126system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
127system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
128system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
129system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
130system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
131system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
132system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
133system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits
134system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits
135system.cpu.icache.overall_hits::total 14928 # number of overall hits
136system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
137system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
138system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
139system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
140system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
141system.cpu.icache.overall_misses::total 280 # number of overall misses
142system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles
143system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles
144system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles
145system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles
146system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles
147system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles
148system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
149system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
150system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
151system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses
152system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses
153system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses
154system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses
155system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses
156system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses
157system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
158system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
159system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
160system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency
161system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency
162system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency
163system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency
164system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency
165system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency
166system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
168system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
169system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
170system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172system.cpu.icache.fast_writes 0 # number of fast writes performed
173system.cpu.icache.cache_copies 0 # number of cache copies performed
174system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
175system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
176system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
177system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
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179system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
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181system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
182system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
183system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
184system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
185system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
186system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
187system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
188system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
189system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
190system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
191system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
192system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
193system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency
194system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
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196system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
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202system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
203system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
204system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
205system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
206system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
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211system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
212system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
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214system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
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--- 7 unchanged lines hidden (view full) ---
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251system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
--- 6 unchanged lines hidden (view full) ---
258system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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267system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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269system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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271system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
272system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
273system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
276system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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279system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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282system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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297system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
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302system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
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304system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
305system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
306system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
307system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
308system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
309system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses
310system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
311system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
312system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
313system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
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315system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
316system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
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318system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
319system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
320system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
321system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
322system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
323system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
324system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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326system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
327system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
328system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
329system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
330system.cpu.dcache.tags.replacements 0 # number of replacements
331system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
332system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
333system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
334system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
335system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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340system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
341system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
342system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
343system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
344system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
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346system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
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348system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
349system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
350system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
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352system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
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354system.cpu.dcache.overall_hits::total 3529 # number of overall hits
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356system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
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362system.cpu.dcache.overall_misses::total 138 # number of overall misses
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366system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
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376system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
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378system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
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380system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
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382system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
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386system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
387system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
388system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
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394system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
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402system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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420system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
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422system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
423system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
424system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
425system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
426system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
427system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
428system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
429system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
430system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
431system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
432system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
433system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
434system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
435system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
436system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
437system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
439system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
440system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
441system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
442system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
443system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
444system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
--- 12 unchanged lines hidden (view full) ---
458system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
459system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
460system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
461system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
462system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
463system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
464system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
465system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
466
467---------- End Simulation Statistics ----------