1Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout 2Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
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3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5
| 1gem5 Simulator System. http://gem5.org 2gem5 is copyrighted software; use the --copyright option for details. 3
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6gem5 compiled Nov 15 2015 15:07:43 7gem5 started Nov 15 2015 15:08:11 8gem5 executing on ribera.cs.wisc.edu, pid 7750 9command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
| 4gem5 compiled Dec 11 2015 20:33:09 5gem5 started Dec 11 2015 20:33:36 6gem5 executing on zizzer, pid 856 7command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
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10 11Global frequency set at 1000000000000 ticks per second 12info: Entering event queue @ 0. Starting simulation... 13Begining test of difficult SPARC instructions... 14LDSTUB: Passed 15SWAP: Passed 16CAS FAIL: Passed 17CAS WORK: Passed 18CASX FAIL: Passed 19CASX WORK: Passed 20LDTX: Passed 21LDTW: Passed 22STTW: Passed 23Done 24Exiting @ tick 44282500 because target called exit()
| 8 9Global frequency set at 1000000000000 ticks per second 10info: Entering event queue @ 0. Starting simulation... 11Begining test of difficult SPARC instructions... 12LDSTUB: Passed 13SWAP: Passed 14CAS FAIL: Passed 15CAS WORK: Passed 16CASX FAIL: Passed 17CASX WORK: Passed 18LDTX: Passed 19LDTW: Passed 20STTW: Passed 21Done 22Exiting @ tick 44282500 because target called exit()
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