| config.ini (9150:a2370fa5c793) | config.ini (9276:a5ede748a1d9) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 |
|
| 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= --- 21 unchanged lines hidden (view full) --- 42function_trace_start=0 43interrupts=system.cpu.interrupts 44itb=system.cpu.itb 45max_insts_all_threads=0 46max_insts_any_thread=0 47max_loads_all_threads=0 48max_loads_any_thread=0 49numThreads=1 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 21 unchanged lines hidden (view full) --- 43function_trace_start=0 44interrupts=system.cpu.interrupts 45itb=system.cpu.itb 46max_insts_all_threads=0 47max_insts_any_thread=0 48max_loads_all_threads=0 49max_loads_any_thread=0 50numThreads=1 |
| 50phase=0 | |
| 51profile=0 52progress_interval=0 53system=system 54tracer=system.cpu.tracer 55workload=system.cpu.workload 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 | 51profile=0 52progress_interval=0 53system=system 54tracer=system.cpu.tracer 55workload=system.cpu.workload 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 |
| 64clock=1 |
|
| 64forward_snoops=true 65hash_delay=1 | 65forward_snoops=true 66hash_delay=1 |
| 67hit_latency=1000 |
|
| 66is_top_level=true | 68is_top_level=true |
| 67latency=1000 | |
| 68max_miss_count=0 69mshrs=10 70prefetch_on_access=false 71prefetcher=Null 72prioritizeRequests=false 73repl=Null | 69max_miss_count=0 70mshrs=10 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null |
| 75response_latency=1000 |
|
| 74size=262144 75subblock_size=0 76system=system 77tgts_per_mshr=5 78trace_addr=0 79two_queue=false 80write_buffers=8 81cpu_side=system.cpu.dcache_port 82mem_side=system.cpu.toL2Bus.slave[1] 83 84[system.cpu.dtb] 85type=SparcTLB 86size=64 87 88[system.cpu.icache] 89type=BaseCache 90addr_ranges=0:18446744073709551615 91assoc=2 92block_size=64 | 76size=262144 77subblock_size=0 78system=system 79tgts_per_mshr=5 80trace_addr=0 81two_queue=false 82write_buffers=8 83cpu_side=system.cpu.dcache_port 84mem_side=system.cpu.toL2Bus.slave[1] 85 86[system.cpu.dtb] 87type=SparcTLB 88size=64 89 90[system.cpu.icache] 91type=BaseCache 92addr_ranges=0:18446744073709551615 93assoc=2 94block_size=64 |
| 95clock=1 |
|
| 93forward_snoops=true 94hash_delay=1 | 96forward_snoops=true 97hash_delay=1 |
| 98hit_latency=1000 |
|
| 95is_top_level=true | 99is_top_level=true |
| 96latency=1000 | |
| 97max_miss_count=0 98mshrs=10 99prefetch_on_access=false 100prefetcher=Null 101prioritizeRequests=false 102repl=Null | 100max_miss_count=0 101mshrs=10 102prefetch_on_access=false 103prefetcher=Null 104prioritizeRequests=false 105repl=Null |
| 106response_latency=1000 |
|
| 103size=131072 104subblock_size=0 105system=system 106tgts_per_mshr=5 107trace_addr=0 108two_queue=false 109write_buffers=8 110cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 117type=SparcTLB 118size=64 119 120[system.cpu.l2cache] 121type=BaseCache 122addr_ranges=0:18446744073709551615 123assoc=2 124block_size=64 | 107size=131072 108subblock_size=0 109system=system 110tgts_per_mshr=5 111trace_addr=0 112two_queue=false 113write_buffers=8 114cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 121type=SparcTLB 122size=64 123 124[system.cpu.l2cache] 125type=BaseCache 126addr_ranges=0:18446744073709551615 127assoc=2 128block_size=64 |
| 129clock=1 |
|
| 125forward_snoops=true 126hash_delay=1 | 130forward_snoops=true 131hash_delay=1 |
| 132hit_latency=10000 |
|
| 127is_top_level=false | 133is_top_level=false |
| 128latency=10000 | |
| 129max_miss_count=0 130mshrs=10 131prefetch_on_access=false 132prefetcher=Null 133prioritizeRequests=false 134repl=Null | 134max_miss_count=0 135mshrs=10 136prefetch_on_access=false 137prefetcher=Null 138prioritizeRequests=false 139repl=Null |
| 140response_latency=10000 |
|
| 135size=2097152 136subblock_size=0 137system=system 138tgts_per_mshr=5 139trace_addr=0 140two_queue=false 141write_buffers=8 142cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 158[system.cpu.workload] 159type=LiveProcess 160cmd=insttest 161cwd= 162egid=100 163env= 164errout=cerr 165euid=100 | 141size=2097152 142subblock_size=0 143system=system 144tgts_per_mshr=5 145trace_addr=0 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 164[system.cpu.workload] 165type=LiveProcess 166cmd=insttest 167cwd= 168egid=100 169env= 170errout=cerr 171euid=100 |
| 166executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest | 172executable=tests/test-progs/insttest/bin/sparc/linux/insttest |
| 167gid=100 168input=cin 169max_stack_size=67108864 170output=cout 171pid=100 172ppid=99 173simpoint=0 174system=system --- 6 unchanged lines hidden (view full) --- 181header_cycles=1 182use_default_range=false 183width=8 184master=system.physmem.port 185slave=system.system_port system.cpu.l2cache.mem_side 186 187[system.physmem] 188type=SimpleMemory | 173gid=100 174input=cin 175max_stack_size=67108864 176output=cout 177pid=100 178ppid=99 179simpoint=0 180system=system --- 6 unchanged lines hidden (view full) --- 187header_cycles=1 188use_default_range=false 189width=8 190master=system.physmem.port 191slave=system.system_port system.cpu.l2cache.mem_side 192 193[system.physmem] 194type=SimpleMemory |
| 195bandwidth=73.000000 196clock=1 |
|
| 189conf_table_reported=false | 197conf_table_reported=false |
| 190file= | |
| 191in_addr_map=true 192latency=30000 193latency_var=0 194null=false 195range=0:134217727 196zero=false 197port=system.membus.master[0] 198 | 198in_addr_map=true 199latency=30000 200latency_var=0 201null=false 202range=0:134217727 203zero=false 204port=system.membus.master[0] 205 |