| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated |
| 4sim_ticks 26524500 # Number of ticks simulated 5final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 26616500 # Number of ticks simulated 5final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 19767 # Simulator instruction rate (inst/s) 8host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36317578 # Simulator tick rate (ticks/s) 10host_mem_usage 236084 # Number of bytes of host memory used 11host_seconds 0.73 # Real time elapsed on the host | 7host_inst_rate 75478 # Simulator instruction rate (inst/s) 8host_op_rate 75473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 139143595 # Simulator tick rate (ticks/s) 10host_mem_usage 260732 # Number of bytes of host memory used 11host_seconds 0.19 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 34system.physmem.bytesRead 30848 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis 56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 74system.physmem.totGap 26363500 # Total gap between requests 75system.physmem.readPktSize::0 0 # Categorize read packet sizes 76system.physmem.readPktSize::1 0 # Categorize read packet sizes 77system.physmem.readPktSize::2 0 # Categorize read packet sizes 78system.physmem.readPktSize::3 0 # Categorize read packet sizes 79system.physmem.readPktSize::4 0 # Categorize read packet sizes 80system.physmem.readPktSize::5 0 # Categorize read packet sizes 81system.physmem.readPktSize::6 482 # Categorize read packet sizes 82system.physmem.writePktSize::0 0 # Categorize write packet sizes 83system.physmem.writePktSize::1 0 # Categorize write packet sizes 84system.physmem.writePktSize::2 0 # Categorize write packet sizes 85system.physmem.writePktSize::3 0 # Categorize write packet sizes 86system.physmem.writePktSize::4 0 # Categorize write packet sizes 87system.physmem.writePktSize::5 0 # Categorize write packet sizes 88system.physmem.writePktSize::6 0 # Categorize write packet sizes | 22system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 482 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 102 # Per bank write bursts 43system.physmem.perBankRdBursts::1 29 # Per bank write bursts 44system.physmem.perBankRdBursts::2 50 # Per bank write bursts 45system.physmem.perBankRdBursts::3 24 # Per bank write bursts 46system.physmem.perBankRdBursts::4 19 # Per bank write bursts 47system.physmem.perBankRdBursts::5 0 # Per bank write bursts 48system.physmem.perBankRdBursts::6 32 # Per bank write bursts 49system.physmem.perBankRdBursts::7 35 # Per bank write bursts 50system.physmem.perBankRdBursts::8 4 # Per bank write bursts 51system.physmem.perBankRdBursts::9 1 # Per bank write bursts 52system.physmem.perBankRdBursts::10 1 # Per bank write bursts 53system.physmem.perBankRdBursts::11 0 # Per bank write bursts 54system.physmem.perBankRdBursts::12 57 # Per bank write bursts 55system.physmem.perBankRdBursts::13 31 # Per bank write bursts 56system.physmem.perBankRdBursts::14 61 # Per bank write bursts 57system.physmem.perBankRdBursts::15 36 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 26455500 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 482 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 89system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see | 91system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see |
| 90system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see | 92system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see |
| 92system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 94system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 153system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation 172system.physmem.totQLat 1755500 # Total cycles spent in queuing delays 173system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests 174system.physmem.totBusLat 2410000 # Total cycles spent in databus access 175system.physmem.totBankLat 6765000 # Total cycles spent in bank access 176system.physmem.avgQLat 3642.12 # Average queueing delay per request 177system.physmem.avgBankLat 14035.27 # Average bank access latency per request 178system.physmem.avgBusLat 5000.00 # Average bus latency per request 179system.physmem.avgMemAccLat 22677.39 # Average memory access latency 180system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s 181system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 182system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s 183system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 184system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 185system.physmem.busUtil 9.09 # Data bus utilization in percentage 186system.physmem.avgRdQLen 0.41 # Average read queue length over time 187system.physmem.avgWrQLen 0.00 # Average write queue length over time 188system.physmem.readRowHits 430 # Number of row buffer hits during reads | 155system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation 178system.physmem.totQLat 2423000 # Total ticks spent queuing 179system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM 180system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers 181system.physmem.totBankLat 6778750 # Total ticks spent accessing banks 182system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst 183system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst 184system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 185system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst 186system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s 187system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 188system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s 189system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 190system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 191system.physmem.busUtil 9.05 # Data bus utilization in percentage 192system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads 193system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 194system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing 195system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 196system.physmem.readRowHits 413 # Number of row buffer hits during reads |
| 189system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 197system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 190system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads | 198system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads |
| 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 199system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 192system.physmem.avgGap 54696.06 # Average gap between requests 193system.membus.throughput 1163000245 # Throughput (bytes/s) | 200system.physmem.avgGap 54886.93 # Average gap between requests 201system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined 202system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state 203system.membus.throughput 1158980332 # Throughput (bytes/s) |
| 194system.membus.trans_dist::ReadReq 399 # Transaction distribution 195system.membus.trans_dist::ReadResp 399 # Transaction distribution 196system.membus.trans_dist::ReadExReq 83 # Transaction distribution 197system.membus.trans_dist::ReadExResp 83 # Transaction distribution 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 202system.membus.data_through_bus 30848 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 204system.membus.trans_dist::ReadReq 399 # Transaction distribution 205system.membus.trans_dist::ReadResp 399 # Transaction distribution 206system.membus.trans_dist::ReadExReq 83 # Transaction distribution 207system.membus.trans_dist::ReadExResp 83 # Transaction distribution 208system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) 209system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 210system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) 211system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 212system.membus.data_through_bus 30848 # Total data (bytes) 213system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 204system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) | 214system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) |
| 205system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) | 215system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) |
| 206system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 17.0 # Layer utilization (%) 208system.cpu.branchPred.lookups 6716 # Number of BP lookups 209system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted | 216system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) 217system.membus.respLayer1.utilization 16.9 # Layer utilization (%) 218system.cpu.branchPred.lookups 6713 # Number of BP lookups 219system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted |
| 210system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect | 220system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect |
| 211system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups | 221system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups |
| 212system.cpu.branchPred.BTBHits 2432 # Number of BTB hits 213system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 222system.cpu.branchPred.BTBHits 2432 # Number of BTB hits 223system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 214system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage | 224system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage |
| 215system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. 216system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 217system.cpu.workload.num_syscalls 18 # Number of system calls | 225system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. 226system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 227system.cpu.workload.num_syscalls 18 # Number of system calls |
| 218system.cpu.numCycles 53050 # number of cpu cycles simulated | 228system.cpu.numCycles 53234 # number of cpu cycles simulated |
| 219system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 220system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 229system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 221system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss 222system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed 223system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered | 231system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss 232system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed 233system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered |
| 224system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken | 234system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken |
| 225system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked | 235system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked |
| 226system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing | 236system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing |
| 227system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked | 237system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked |
| 228system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 238system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 229system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps 230system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched | 239system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps 240system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched |
| 231system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed | 241system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed |
| 232system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) | 242system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total) |
| 235system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 245system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 236system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) | 246system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total) |
| 245system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 255system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 248system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle 250system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle 251system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle 252system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked 253system.cpu.decode.RunCycles 8344 # Number of cycles decode is running | 258system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle 260system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle 261system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle 262system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked 263system.cpu.decode.RunCycles 8343 # Number of cycles decode is running |
| 254system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking 255system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing | 264system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking 265system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing |
| 256system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode | 266system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode |
| 257system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing | 267system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing |
| 258system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle | 268system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle |
| 259system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking | 269system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking |
| 260system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst | 270system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst |
| 261system.cpu.rename.RunCycles 7952 # Number of cycles rename is running 262system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking 263system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename 264system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 265system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full 266system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed 267system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made 268system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups --- 8 unchanged lines hidden (view full) --- 277system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 278system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) 279system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ 280system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued 281system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued 282system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling 283system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph 284system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed | 271system.cpu.rename.RunCycles 7952 # Number of cycles rename is running 272system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking 273system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename 274system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 275system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full 276system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed 277system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made 278system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups --- 8 unchanged lines hidden (view full) --- 287system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 288system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) 289system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ 290system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued 291system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued 292system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling 293system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph 294system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed |
| 285system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle | 295system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle |
| 288system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 298system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 289system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle 293system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle | 299system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle 303system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle |
| 294system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle 295system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle 298system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 299system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 304system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 301system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle | 311system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle |
| 302system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 303system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available 304system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available 305system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available 306system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available 307system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available 308system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available 309system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 363system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued 366system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued 367system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued 368system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 369system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 370system.cpu.iq.FU_type_0::total 21122 # Type of FU issued | 312system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 313system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available 314system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available 315system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available 316system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available 317system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available 318system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available 319system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 373system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued 376system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued 377system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued 378system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 379system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 380system.cpu.iq.FU_type_0::total 21122 # Type of FU issued |
| 371system.cpu.iq.rate 0.398153 # Inst issue rate | 381system.cpu.iq.rate 0.396776 # Inst issue rate |
| 372system.cpu.iq.fu_busy_cnt 147 # FU busy when requested 373system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) | 382system.cpu.iq.fu_busy_cnt 147 # FU busy when requested 383system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) |
| 374system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads | 384system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads |
| 375system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes 376system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses 377system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 378system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 379system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 380system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses 381system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 382system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 407system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions 408system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed 409system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute 410system.cpu.iew.exec_swp 0 # number of swp insts executed 411system.cpu.iew.exec_nop 1134 # number of nop insts executed 412system.cpu.iew.exec_refs 5224 # number of memory reference insts executed 413system.cpu.iew.exec_branches 4239 # Number of branches executed 414system.cpu.iew.exec_stores 2022 # Number of stores executed | 385system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes 386system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses 387system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 388system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 389system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 390system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses 391system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 392system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 417system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions 418system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed 419system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute 420system.cpu.iew.exec_swp 0 # number of swp insts executed 421system.cpu.iew.exec_nop 1134 # number of nop insts executed 422system.cpu.iew.exec_refs 5224 # number of memory reference insts executed 423system.cpu.iew.exec_branches 4239 # Number of branches executed 424system.cpu.iew.exec_stores 2022 # Number of stores executed |
| 415system.cpu.iew.exec_rate 0.378398 # Inst execution rate | 425system.cpu.iew.exec_rate 0.377090 # Inst execution rate |
| 416system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit 417system.cpu.iew.wb_count 19522 # cumulative count of insts written-back 418system.cpu.iew.wb_producers 9120 # num instructions producing a value 419system.cpu.iew.wb_consumers 11235 # num instructions consuming a value 420system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 426system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit 427system.cpu.iew.wb_count 19522 # cumulative count of insts written-back 428system.cpu.iew.wb_producers 9120 # num instructions producing a value 429system.cpu.iew.wb_consumers 11235 # num instructions consuming a value 430system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 421system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle | 431system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle |
| 422system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back 423system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 424system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit 425system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 426system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted | 432system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back 433system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 434system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit 435system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 436system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted |
| 427system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle | 437system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle 439system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle |
| 430system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 440system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 431system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle 435system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle | 441system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle 445system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle |
| 436system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle 437system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle | 446system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle |
| 438system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle | 448system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle |
| 439system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle 440system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 441system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 449system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 443system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle | 453system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle |
| 444system.cpu.commit.committedInsts 15162 # Number of instructions committed 445system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 446system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 447system.cpu.commit.refs 3673 # Number of memory references committed 448system.cpu.commit.loads 2225 # Number of loads committed 449system.cpu.commit.membars 0 # Number of memory barriers committed 450system.cpu.commit.branches 3358 # Number of branches committed 451system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 452system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 453system.cpu.commit.function_calls 187 # Number of function calls committed. 454system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 455system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 454system.cpu.commit.committedInsts 15162 # Number of instructions committed 455system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 456system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 457system.cpu.commit.refs 3673 # Number of memory references committed 458system.cpu.commit.loads 2225 # Number of loads committed 459system.cpu.commit.membars 0 # Number of memory barriers committed 460system.cpu.commit.branches 3358 # Number of branches committed 461system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 462system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 463system.cpu.commit.function_calls 187 # Number of function calls committed. 464system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 465system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 456system.cpu.rob.rob_reads 54596 # The number of ROB reads | 466system.cpu.rob.rob_reads 54530 # The number of ROB reads |
| 457system.cpu.rob.rob_writes 50298 # The number of ROB writes | 467system.cpu.rob.rob_writes 50298 # The number of ROB writes |
| 458system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself 459system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling | 468system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself 469system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 460system.cpu.committedInsts 14436 # Number of Instructions Simulated 461system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 462system.cpu.committedInsts_total 14436 # Number of Instructions Simulated | 470system.cpu.committedInsts 14436 # Number of Instructions Simulated 471system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 472system.cpu.committedInsts_total 14436 # Number of Instructions Simulated |
| 463system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction 464system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads 465system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle 466system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads | 473system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction 474system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads 475system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle 476system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads |
| 467system.cpu.int_regfile_reads 32043 # number of integer regfile reads 468system.cpu.int_regfile_writes 17841 # number of integer regfile writes 469system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 470system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 477system.cpu.int_regfile_reads 32043 # number of integer regfile reads 478system.cpu.int_regfile_writes 17841 # number of integer regfile writes 479system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 480system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 471system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) | 481system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s) |
| 472system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 479system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) 482system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 483system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 484system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 485system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 482system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 485system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 486system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) 487system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 488system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 489system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) 490system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 491system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) 492system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 493system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 494system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 495system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 486system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) | 496system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks) |
| 487system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) | 497system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) |
| 488system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) | 498system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) |
| 489system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 490system.cpu.icache.tags.replacements 0 # number of replacements | 499system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 500system.cpu.icache.tags.replacements 0 # number of replacements |
| 491system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use 492system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. | 501system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use 502system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. |
| 493system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. | 503system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. |
| 494system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. | 504system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. |
| 495system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 505system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 496system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor 497system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy 498system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy 499system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits 500system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits 501system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits 502system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits 503system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits 504system.cpu.icache.overall_hits::total 4873 # number of overall hits | 506system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor 507system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy 508system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy 509system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits 510system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits 511system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits 512system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits 513system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits 514system.cpu.icache.overall_hits::total 4872 # number of overall hits |
| 505system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 506system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses 507system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses 508system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses 509system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses 510system.cpu.icache.overall_misses::total 507 # number of overall misses | 515system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 516system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses 517system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses 518system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses 519system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses 520system.cpu.icache.overall_misses::total 507 # number of overall misses |
| 511system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles 512system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles 513system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles 514system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles 515system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles 516system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles 517system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) 518system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) 519system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses 520system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses 521system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses 522system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses 523system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses 524system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses 525system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses 526system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses 527system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses 528system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses 529system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency 530system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency 531system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency 532system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency 533system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency 534system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency | 521system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles 522system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles 523system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles 524system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles 525system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles 526system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles 527system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) 528system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) 529system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses 530system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses 531system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses 532system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses 533system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses 535system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses 536system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses 537system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses 538system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses 539system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency 540system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency 541system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency 542system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency 543system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency 544system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency |
| 535system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 539system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 541system.cpu.icache.fast_writes 0 # number of fast writes performed 542system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 547system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits 548system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits 549system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 550system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses 551system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 552system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses 553system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 554system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses | 545system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu.icache.fast_writes 0 # number of fast writes performed 552system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 557system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits 558system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits 559system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 560system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses 561system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 562system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses 563system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 564system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses |
| 555system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles 556system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles 557system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles 558system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles 559system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles 560system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles 561system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses 562system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses 563system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses 564system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses 565system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses 566system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses 567system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency 568system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency 569system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 570system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency 571system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 572system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency | 565system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles 566system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles 567system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles 568system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles 569system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles 570system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles 571system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses 572system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses 573system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses 574system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses 575system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses 576system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses 577system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency 578system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency 579system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency 580system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency 581system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency 582system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency |
| 573system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 574system.cpu.l2cache.tags.replacements 0 # number of replacements | 583system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 584system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 575system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use | 585system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use |
| 576system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 577system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 578system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 579system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 586system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 587system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 588system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 589system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 580system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor 581system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor 582system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy | 590system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor 591system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor 592system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy |
| 583system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy | 593system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy |
| 584system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy | 594system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy |
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| 602system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles 604system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles 605system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles 606system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles 607system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles 609system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles 610system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles 611system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles 612system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles | 612system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles 613system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles 614system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles 615system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles 616system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles 617system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles 618system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles 619system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles 620system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles 621system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles 622system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles |
| 613system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 615system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 616system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 617system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 618system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses 619system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 620system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 627system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 628system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 629system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses 630system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 631system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses 632system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses 633system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 634system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses | 623system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) 624system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 625system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 626system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 627system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 628system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses 629system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 630system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 637system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 638system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 639system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses 640system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 641system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses 642system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses 643system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 644system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses |
| 635system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency 636system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency 637system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency 638system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency 639system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency 642system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency 645system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency | 645system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency 646system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency 647system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency 648system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency 649system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency 650system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency 651system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency 652system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency 653system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency 655system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency |
| 646system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 648system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 649system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 650system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 651system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 652system.cpu.l2cache.fast_writes 0 # number of fast writes performed 653system.cpu.l2cache.cache_copies 0 # number of cache copies performed 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 655system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 656system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 664system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses | 656system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.l2cache.fast_writes 0 # number of fast writes performed 663system.cpu.l2cache.cache_copies 0 # number of cache copies performed 664system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 665system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 666system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 667system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 668system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 669system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 670system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 671system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses 672system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 673system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 674system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses |
| 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles | 675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles 677system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles 678system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles 679system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles 685system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles |
| 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 678system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 683system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 686system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses | 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 688system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 690system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses 692system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 693system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses 694system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses 695system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 696system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses |
| 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency | 697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency 698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency 699system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency 700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency 701system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency 702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency 703system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency 704system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency 705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency 706system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency 707system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency |
| 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699system.cpu.dcache.tags.replacements 0 # number of replacements | 708system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 709system.cpu.dcache.tags.replacements 0 # number of replacements |
| 700system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use | 710system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use |
| 701system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 702system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 703system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 704system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 711system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 712system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 713system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 714system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 705system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor 706system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy 707system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy | 715system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor 716system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy 717system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy |
| 708system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 709system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits 710system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 711system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 712system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 713system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 714system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits 715system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits 716system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits 717system.cpu.dcache.overall_hits::total 3995 # number of overall hits 718system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 719system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 720system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 721system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 722system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses 723system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses 724system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses 725system.cpu.dcache.overall_misses::total 535 # number of overall misses | 718system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 719system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits 720system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 721system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 722system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 723system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 724system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits 725system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits 726system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits 727system.cpu.dcache.overall_hits::total 3995 # number of overall hits 728system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 729system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 730system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 731system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 732system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses 733system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses 734system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses 735system.cpu.dcache.overall_misses::total 535 # number of overall misses |
| 726system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles 727system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles 728system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles 729system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles 730system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles 731system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles 732system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles 733system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles | 736system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles 737system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles 738system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles 739system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles 740system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles 741system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles 742system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles 743system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles |
| 734system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) 735system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) 736system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 737system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 738system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 739system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 740system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses 741system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses 742system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses 743system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses 744system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses 745system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses 746system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 747system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 748system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses 749system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses 750system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses 751system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses | 744system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) 745system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) 746system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 747system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 748system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 749system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 750system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses 751system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses 752system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses 753system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses 754system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses 755system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses 756system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 757system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 758system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses 759system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses 760system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses 761system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses |
| 752system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency 753system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency 754system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency 755system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency 756system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency 757system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency 758system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency 759system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency | 762system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency 763system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency 764system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency 765system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency 766system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency 767system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency 768system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency 769system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency |
| 760system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked 761system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 763system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked 765system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.dcache.fast_writes 0 # number of fast writes performed 767system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 776system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 777system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 778system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 779system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 780system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 781system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 782system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 783system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 770system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked 771system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 773system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked 775system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu.dcache.fast_writes 0 # number of fast writes performed 777system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 786system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 787system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 789system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 790system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 791system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 792system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 793system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 784system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles 785system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles 786system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles 787system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles 788system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles 789system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles 790system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles 791system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles | 794system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles 795system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles 796system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles 797system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles 798system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles 799system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles 800system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles 801system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles |
| 792system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses 793system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses 794system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 795system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 796system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses 797system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses 798system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses 799system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses | 802system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses 803system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses 804system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 805system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 806system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses 807system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses 808system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses 809system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses |
| 800system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency 801system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency 802system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency 803system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency 805system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency 807system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency | 810system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency 811system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency 812system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency 813system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency 814system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency 815system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency 816system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency 817system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency |
| 808system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 809 810---------- End Simulation Statistics ---------- | 818system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 819 820---------- End Simulation Statistics ---------- |