| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 26524500 # Number of ticks simulated 5final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 26524500 # Number of ticks simulated 5final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 52714 # Simulator instruction rate (inst/s) 8host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 96835127 # Simulator tick rate (ticks/s) 10host_mem_usage 234512 # Number of bytes of host memory used 11host_seconds 0.27 # Real time elapsed on the host | 7host_inst_rate 95044 # Simulator instruction rate (inst/s) 8host_op_rate 95035 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 174603061 # Simulator tick rate (ticks/s) 10host_mem_usage 232868 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 482 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady | 30system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 33system.physmem.bytesRead 30848 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() | 34system.physmem.bytesRead 30848 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q |
| 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 189system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap 54696.06 # Average gap between requests 192system.membus.throughput 1163000245 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 399 # Transaction distribution 194system.membus.trans_dist::ReadResp 399 # Transaction distribution 195system.membus.trans_dist::ReadExReq 83 # Transaction distribution 196system.membus.trans_dist::ReadExResp 83 # Transaction distribution | 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 190system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 54696.06 # Average gap between requests 193system.membus.throughput 1163000245 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 399 # Transaction distribution 195system.membus.trans_dist::ReadResp 399 # Transaction distribution 196system.membus.trans_dist::ReadExReq 83 # Transaction distribution 197system.membus.trans_dist::ReadExResp 83 # Transaction distribution |
| 197system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 964 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) | 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) |
| 201system.membus.data_through_bus 30848 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 205system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 17.0 # Layer utilization (%) 207system.cpu.branchPred.lookups 6716 # Number of BP lookups 208system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted --- 258 unchanged lines hidden (view full) --- 467system.cpu.int_regfile_writes 17841 # number of integer regfile writes 468system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 469system.cpu.misc_regfile_writes 569 # number of misc regfile writes 470system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) 471system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution | 202system.membus.data_through_bus 30848 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 206system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 17.0 # Layer utilization (%) 208system.cpu.branchPred.lookups 6716 # Number of BP lookups 209system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted --- 258 unchanged lines hidden (view full) --- 468system.cpu.int_regfile_writes 17841 # number of integer regfile writes 469system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 470system.cpu.misc_regfile_writes 569 # number of misc regfile writes 471system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) 472system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution |
| 475system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes) 479system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes) | 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 479system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) |
| 481system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 482system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 483system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 484system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 485system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) 486system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 482system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 483system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 484system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 485system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 486system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) 487system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 488system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) 489system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 489system.cpu.icache.tags.replacements 0 # number of replacements 490system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use 491system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. 492system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. 493system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. 494system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 495system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor 496system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy 497system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy | 490system.cpu.icache.tags.replacements 0 # number of replacements 491system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use 492system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. 493system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. 494system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. 495system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 496system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor 497system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy 498system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy |
| 498system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits 499system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits 500system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits 501system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits 502system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits 503system.cpu.icache.overall_hits::total 4873 # number of overall hits 504system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 505system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 565system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency 567system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 569system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 571system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency 572system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 499system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits 500system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits 501system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits 502system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits 503system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits 504system.cpu.icache.overall_hits::total 4873 # number of overall hits 505system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 506system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 566system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses 567system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency 568system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency 569system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 570system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency 571system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency 572system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency 573system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 573system.cpu.l2cache.tags.replacements 0 # number of replacements 574system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use 575system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 576system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 577system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 578system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 579system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor 580system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor | 574system.cpu.l2cache.tags.replacements 0 # number of replacements 575system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use 576system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 577system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 578system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 579system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 580system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor 581system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor |
| 581system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy 582system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy | 582system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy 583system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy |
| 583system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy | 584system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy |
| 584system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 585system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 586system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 587system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 588system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 589system.cpu.l2cache.overall_hits::total 2 # number of overall hits 590system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 591system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses --- 98 unchanged lines hidden (view full) --- 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 585system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 586system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 587system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 588system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 589system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 590system.cpu.l2cache.overall_hits::total 2 # number of overall hits 591system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 592system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses --- 98 unchanged lines hidden (view full) --- 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 698system.cpu.dcache.tags.replacements 0 # number of replacements 699system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use 700system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 701system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 702system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 703system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 704system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor 705system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy 706system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy | 699system.cpu.dcache.tags.replacements 0 # number of replacements 700system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use 701system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 702system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 703system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 704system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 705system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor 706system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy 707system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy |
| 707system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits 709system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 711system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 712system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 713system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits 714system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits --- 95 unchanged lines hidden --- | 708system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 709system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits 710system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 711system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 712system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 713system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 714system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits 715system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits --- 95 unchanged lines hidden --- |