| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23775500 # Number of ticks simulated 5final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26399500 # Number of ticks simulated 5final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 12604 # Simulator instruction rate (inst/s) 8host_op_rate 12604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20757401 # Simulator tick rate (ticks/s) 10host_mem_usage 277264 # Number of bytes of host memory used 11host_seconds 1.15 # Real time elapsed on the host | 7host_inst_rate 93938 # Simulator instruction rate (inst/s) 8host_op_rate 93929 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171756334 # Simulator tick rate (ticks/s) 10host_mem_usage 234512 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory | 16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory |
| 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory | 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory |
| 21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 483 # Total number of read requests seen | 21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 482 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30912 # Total number of bytes read from memory | 32system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30848 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 23715500 # Total gap between requests | 73system.physmem.totGap 26239500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 483 # Categorize read packet sizes | 80system.physmem.readPktSize::6 482 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see |
| 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 4632000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests 154system.physmem.totBusLat 2415000 # Total cycles spent in databus access 155system.physmem.totBankLat 8566250 # Total cycles spent in bank access 156system.physmem.avgQLat 9590.06 # Average queueing delay per request 157system.physmem.avgBankLat 17735.51 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation 171system.physmem.totQLat 1765750 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests 173system.physmem.totBusLat 2410000 # Total cycles spent in databus access 174system.physmem.totBankLat 6751250 # Total cycles spent in bank access 175system.physmem.avgQLat 3663.38 # Average queueing delay per request 176system.physmem.avgBankLat 14006.74 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 32325.57 # Average memory access latency 160system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s | 178system.physmem.avgMemAccLat 22670.12 # Average memory access latency 179system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s | 181system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 10.16 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.66 # Average read queue length over time | 184system.physmem.busUtil 9.13 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.41 # Average read queue length over time |
| 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 186system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 369 # Number of row buffer hits during reads | 187system.physmem.readRowHits 430 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads | 189system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 49100.41 # Average gap between requests 173system.cpu.branchPred.lookups 6770 # Number of BP lookups 174system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 2447 # Number of BTB hits | 191system.physmem.avgGap 54438.80 # Average gap between requests 192system.membus.throughput 1168506979 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 399 # Transaction distribution 194system.membus.trans_dist::ReadResp 399 # Transaction distribution 195system.membus.trans_dist::ReadExReq 83 # Transaction distribution 196system.membus.trans_dist::ReadExResp 83 # Transaction distribution 197system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 964 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) 201system.membus.data_through_bus 30848 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) 205system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 17.0 # Layer utilization (%) 207system.cpu.branchPred.lookups 6719 # Number of BP lookups 208system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted 209system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect 210system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups 211system.cpu.branchPred.BTBHits 2433 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 212system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. | 213system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage 214system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. |
| 181system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 182system.cpu.workload.num_syscalls 18 # Number of system calls | 215system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 216system.cpu.workload.num_syscalls 18 # Number of system calls |
| 183system.cpu.numCycles 47552 # number of cpu cycles simulated | 217system.cpu.numCycles 52800 # number of cpu cycles simulated |
| 184system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 185system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 218system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 219system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 186system.cpu.fetch.icacheStallCycles 12221 # Number of cycles fetch is stalled on an Icache miss 187system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed 188system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered 189system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken 190system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked 191system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing 192system.cpu.fetch.BlockedCycles 8387 # Number of cycles fetch has spent blocked | 220system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss 221system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed 222system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered 223system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken 224system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked 225system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing 226system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked |
| 193system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 227system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 194system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps 195system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched 196system.cpu.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed 197system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) 198system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) 199system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) | 228system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps 229system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched 230system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed 231system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total) |
| 200system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 234system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 201system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) 204system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) | 235system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) |
| 210system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 244system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 213system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle 215system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle 216system.cpu.decode.IdleCycles 12951 # Number of cycles decode is idle 217system.cpu.decode.BlockedCycles 9300 # Number of cycles decode is blocked 218system.cpu.decode.RunCycles 8402 # Number of cycles decode is running 219system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking 220system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing 221system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode 222system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing 223system.cpu.rename.IdleCycles 13601 # Number of cycles rename is idle 224system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking 225system.cpu.rename.serializeStallCycles 8395 # count of cycles rename stalled for serializing inst 226system.cpu.rename.RunCycles 8002 # Number of cycles rename is running 227system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking 228system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename 229system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 230system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full 231system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed 232system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made 233system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups | 247system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle 249system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle 250system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle 251system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked 252system.cpu.decode.RunCycles 8340 # Number of cycles decode is running 253system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking 254system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing 255system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode 256system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing 257system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle 258system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking 259system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst 260system.cpu.rename.RunCycles 7953 # Number of cycles rename is running 261system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking 262system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename 263system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 264system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full 265system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed 266system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made 267system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups |
| 234system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed | 268system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed |
| 235system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing | 269system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing |
| 236system.cpu.rename.serializingInsts 691 # count of serializing insts renamed | 270system.cpu.rename.serializingInsts 691 # count of serializing insts renamed |
| 237system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed 238system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer 239system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. 240system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. | 271system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed 272system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer 273system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit. 274system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit. |
| 241system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 242system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 275system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 276system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 243system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) 244system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ 245system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued 246system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued 247system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling 248system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph 249system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed 250system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle 251system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle 252system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle | 277system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec) 278system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ 279system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued 280system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued 281system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling 282system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph 283system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed 284system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle |
| 253system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 287system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 254system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle 255system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle 256system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle 257system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle 258system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle 259system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle | 288system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle 293system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle 294system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle 295system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle |
| 263system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 297system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 298system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 299system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 266system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle | 300system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle |
| 267system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 301system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 268system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available 269system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available 270system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available 271system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available 272system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available 273system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available 274system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available 275system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.41% # attempts to use FU when none available 276system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.41% # attempts to use FU when none available 277system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.41% # attempts to use FU when none available 278system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.41% # attempts to use FU when none available 279system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.41% # attempts to use FU when none available 280system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.41% # attempts to use FU when none available 281system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.41% # attempts to use FU when none available 282system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.41% # attempts to use FU when none available 283system.cpu.iq.fu_full::SimdMult 0 0.00% 29.41% # attempts to use FU when none available 284system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.41% # attempts to use FU when none available 285system.cpu.iq.fu_full::SimdShift 0 0.00% 29.41% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.41% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.41% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.41% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.41% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.41% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.41% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.41% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.41% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available 297system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available 298system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available | 302system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available 303system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available 304system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available 305system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available 306system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available 307system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available 308system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available 309system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available 310system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available 323system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available 331system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available 332system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available |
| 299system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 300system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 301system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 333system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 334system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 335system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 302system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued | 336system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued |
| 303system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued 304system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued 305system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued 306system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued 307system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued 308system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued 309system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued 310system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 323system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued | 337system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued 338system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued 339system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued 340system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued 341system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued 342system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued 343system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued 344system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 357system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued 358system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued 359system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued |
| 331system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued 332system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued | 365system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued 366system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued |
| 333system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 334system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 367system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 368system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 335system.cpu.iq.FU_type_0::total 21278 # Type of FU issued 336system.cpu.iq.rate 0.447468 # Inst issue rate 337system.cpu.iq.fu_busy_cnt 153 # FU busy when requested 338system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) 339system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads 340system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes 341system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses | 369system.cpu.iq.FU_type_0::total 21113 # Type of FU issued 370system.cpu.iq.rate 0.399867 # Inst issue rate 371system.cpu.iq.fu_busy_cnt 147 # FU busy when requested 372system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst) 373system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads 374system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes 375system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses |
| 342system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 343system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 344system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 376system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 377system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 378system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 345system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses | 379system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses |
| 346system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses | 380system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses |
| 347system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores | 381system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores |
| 348system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 382system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 349system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed | 383system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed |
| 350system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 351system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations | 384system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 385system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations |
| 352system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed | 386system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed |
| 353system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 354system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 355system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 356system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked 357system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 387system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 388system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 389system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 390system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked 391system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 358system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing 359system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking 360system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking 361system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ 362system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch 363system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions 364system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions 365system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions 366system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall | 392system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing 393system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking 394system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking 395system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ 396system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch 397system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions 398system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions 399system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions 400system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall |
| 367system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 368system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations | 401system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 402system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations |
| 369system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly | 403system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly |
| 370system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly | 404system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly |
| 371system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute 372system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions 373system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed 374system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute | 405system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute 406system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions 407system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed 408system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute |
| 375system.cpu.iew.exec_swp 0 # number of swp insts executed | 409system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 376system.cpu.iew.exec_nop 1136 # number of nop insts executed 377system.cpu.iew.exec_refs 5272 # number of memory reference insts executed 378system.cpu.iew.exec_branches 4246 # Number of branches executed 379system.cpu.iew.exec_stores 2053 # Number of stores executed 380system.cpu.iew.exec_rate 0.424882 # Inst execution rate 381system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit 382system.cpu.iew.wb_count 19647 # cumulative count of insts written-back 383system.cpu.iew.wb_producers 9208 # num instructions producing a value 384system.cpu.iew.wb_consumers 11364 # num instructions consuming a value | 410system.cpu.iew.exec_nop 1134 # number of nop insts executed 411system.cpu.iew.exec_refs 5224 # number of memory reference insts executed 412system.cpu.iew.exec_branches 4238 # Number of branches executed 413system.cpu.iew.exec_stores 2022 # Number of stores executed 414system.cpu.iew.exec_rate 0.380076 # Inst execution rate 415system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit 416system.cpu.iew.wb_count 19513 # cumulative count of insts written-back 417system.cpu.iew.wb_producers 9111 # num instructions producing a value 418system.cpu.iew.wb_consumers 11226 # num instructions consuming a value |
| 385system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 419system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 386system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle 387system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back | 420system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle 421system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back |
| 388system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 422system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 389system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit | 423system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit |
| 390system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards | 424system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards |
| 391system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted 392system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle 393system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle 394system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle | 425system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted 426system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle |
| 395system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 429system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 396system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle 398system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle | 430system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle 435system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle 436system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle 437system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle |
| 405system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 439system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 440system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 441system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 408system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle | 442system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle |
| 409system.cpu.commit.committedInsts 15162 # Number of instructions committed 410system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 411system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 412system.cpu.commit.refs 3673 # Number of memory references committed 413system.cpu.commit.loads 2225 # Number of loads committed 414system.cpu.commit.membars 0 # Number of memory barriers committed 415system.cpu.commit.branches 3358 # Number of branches committed 416system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 417system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 418system.cpu.commit.function_calls 187 # Number of function calls committed. | 443system.cpu.commit.committedInsts 15162 # Number of instructions committed 444system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 445system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 446system.cpu.commit.refs 3673 # Number of memory references committed 447system.cpu.commit.loads 2225 # Number of loads committed 448system.cpu.commit.membars 0 # Number of memory barriers committed 449system.cpu.commit.branches 3358 # Number of branches committed 450system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 451system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 452system.cpu.commit.function_calls 187 # Number of function calls committed. |
| 419system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached | 453system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached |
| 420system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 454system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 421system.cpu.rob.rob_reads 54359 # The number of ROB reads 422system.cpu.rob.rob_writes 50813 # The number of ROB writes 423system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself 424system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling | 455system.cpu.rob.rob_reads 54580 # The number of ROB reads 456system.cpu.rob.rob_writes 50280 # The number of ROB writes 457system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself 458system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 425system.cpu.committedInsts 14436 # Number of Instructions Simulated 426system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 427system.cpu.committedInsts_total 14436 # Number of Instructions Simulated | 459system.cpu.committedInsts 14436 # Number of Instructions Simulated 460system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 461system.cpu.committedInsts_total 14436 # Number of Instructions Simulated |
| 428system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction 429system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads 430system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle 431system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads 432system.cpu.int_regfile_reads 32289 # number of integer regfile reads 433system.cpu.int_regfile_writes 17967 # number of integer regfile writes 434system.cpu.misc_regfile_reads 6962 # number of misc regfile reads | 462system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction 463system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads 464system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle 465system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads 466system.cpu.int_regfile_reads 32029 # number of integer regfile reads 467system.cpu.int_regfile_writes 17831 # number of integer regfile writes 468system.cpu.misc_regfile_reads 6919 # number of misc regfile reads |
| 435system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 469system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 470system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s) 471system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 475system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes) 479system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 482system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 483system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 484system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 485system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks) 486system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
|
| 436system.cpu.icache.replacements 0 # number of replacements | 489system.cpu.icache.replacements 0 # number of replacements |
| 437system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use 438system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. 439system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. 440system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. | 490system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use 491system.cpu.icache.total_refs 4874 # Total number of references to valid blocks. 492system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. 493system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks. |
| 441system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 494system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 442system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor 443system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy 444system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy 445system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits 446system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits 447system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits 448system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits 449system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits 450system.cpu.icache.overall_hits::total 4850 # number of overall hits 451system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses 452system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses 453system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses 454system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses 455system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses 456system.cpu.icache.overall_misses::total 491 # number of overall misses 457system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles 458system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles 459system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles 460system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles 461system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles 462system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles 463system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) 464system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) 465system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses 466system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses 467system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses 468system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses 469system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses 470system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses 471system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses 472system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses 473system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses 474system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses 475system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency 476system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency 477system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency 478system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency 479system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency 480system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency | 495system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor 496system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy 497system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy 498system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits 499system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits 500system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits 501system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits 502system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits 503system.cpu.icache.overall_hits::total 4874 # number of overall hits 504system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 505system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses 506system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses 507system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses 508system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses 509system.cpu.icache.overall_misses::total 507 # number of overall misses 510system.cpu.icache.ReadReq_miss_latency::cpu.inst 30807500 # number of ReadReq miss cycles 511system.cpu.icache.ReadReq_miss_latency::total 30807500 # number of ReadReq miss cycles 512system.cpu.icache.demand_miss_latency::cpu.inst 30807500 # number of demand (read+write) miss cycles 513system.cpu.icache.demand_miss_latency::total 30807500 # number of demand (read+write) miss cycles 514system.cpu.icache.overall_miss_latency::cpu.inst 30807500 # number of overall miss cycles 515system.cpu.icache.overall_miss_latency::total 30807500 # number of overall miss cycles 516system.cpu.icache.ReadReq_accesses::cpu.inst 5381 # number of ReadReq accesses(hits+misses) 517system.cpu.icache.ReadReq_accesses::total 5381 # number of ReadReq accesses(hits+misses) 518system.cpu.icache.demand_accesses::cpu.inst 5381 # number of demand (read+write) accesses 519system.cpu.icache.demand_accesses::total 5381 # number of demand (read+write) accesses 520system.cpu.icache.overall_accesses::cpu.inst 5381 # number of overall (read+write) accesses 521system.cpu.icache.overall_accesses::total 5381 # number of overall (read+write) accesses 522system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094220 # miss rate for ReadReq accesses 523system.cpu.icache.ReadReq_miss_rate::total 0.094220 # miss rate for ReadReq accesses 524system.cpu.icache.demand_miss_rate::cpu.inst 0.094220 # miss rate for demand accesses 525system.cpu.icache.demand_miss_rate::total 0.094220 # miss rate for demand accesses 526system.cpu.icache.overall_miss_rate::cpu.inst 0.094220 # miss rate for overall accesses 527system.cpu.icache.overall_miss_rate::total 0.094220 # miss rate for overall accesses 528system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60764.299803 # average ReadReq miss latency 529system.cpu.icache.ReadReq_avg_miss_latency::total 60764.299803 # average ReadReq miss latency 530system.cpu.icache.demand_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency 531system.cpu.icache.demand_avg_miss_latency::total 60764.299803 # average overall miss latency 532system.cpu.icache.overall_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency 533system.cpu.icache.overall_avg_miss_latency::total 60764.299803 # average overall miss latency |
| 481system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 482system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 483system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 484system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 485system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 486system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 487system.cpu.icache.fast_writes 0 # number of fast writes performed 488system.cpu.icache.cache_copies 0 # number of cache copies performed | 534system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.icache.fast_writes 0 # number of fast writes performed 541system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 489system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits 490system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits 491system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits 492system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits 493system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits 494system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits 495system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 496system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 497system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 498system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 499system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 500system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 501system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles 502system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles 503system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles 504system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles 505system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles 506system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles 507system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses 508system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses 509system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses 510system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses 511system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses 512system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses 513system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency 514system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency 515system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency 516system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency 517system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency 518system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency | 542system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits 543system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits 544system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits 545system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits 546system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits 547system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits 548system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 549system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses 550system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 551system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses 552system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 553system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses 554system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22247500 # number of ReadReq MSHR miss cycles 555system.cpu.icache.ReadReq_mshr_miss_latency::total 22247500 # number of ReadReq MSHR miss cycles 556system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22247500 # number of demand (read+write) MSHR miss cycles 557system.cpu.icache.demand_mshr_miss_latency::total 22247500 # number of demand (read+write) MSHR miss cycles 558system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22247500 # number of overall MSHR miss cycles 559system.cpu.icache.overall_mshr_miss_latency::total 22247500 # number of overall MSHR miss cycles 560system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for ReadReq accesses 561system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062628 # mshr miss rate for ReadReq accesses 562system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for demand accesses 563system.cpu.icache.demand_mshr_miss_rate::total 0.062628 # mshr miss rate for demand accesses 564system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for overall accesses 565system.cpu.icache.overall_mshr_miss_rate::total 0.062628 # mshr miss rate for overall accesses 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66016.320475 # average ReadReq mshr miss latency 567system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66016.320475 # average ReadReq mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency 569system.cpu.icache.demand_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency 571system.cpu.icache.overall_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency |
| 519system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 520system.cpu.l2cache.replacements 0 # number of replacements | 572system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.l2cache.replacements 0 # number of replacements |
| 521system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use | 574system.cpu.l2cache.tagsinuse 221.715806 # Cycle average of tags in use |
| 522system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. | 575system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. |
| 523system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. 524system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. | 576system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. 577system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks. |
| 525system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 578system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 526system.cpu.l2cache.occ_blocks::cpu.inst 189.932236 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_blocks::cpu.data 34.709985 # Average occupied blocks per requestor 528system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy | 579system.cpu.l2cache.occ_blocks::cpu.inst 187.205303 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_blocks::cpu.data 34.510503 # Average occupied blocks per requestor 581system.cpu.l2cache.occ_percent::cpu.inst 0.005713 # Average percentage of cache occupancy 582system.cpu.l2cache.occ_percent::cpu.data 0.001053 # Average percentage of cache occupancy 583system.cpu.l2cache.occ_percent::total 0.006766 # Average percentage of cache occupancy |
| 531system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 532system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 533system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 534system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 535system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 536system.cpu.l2cache.overall_hits::total 2 # number of overall hits | 584system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 585system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 586system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 587system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 588system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 589system.cpu.l2cache.overall_hits::total 2 # number of overall hits |
| 537system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses | 590system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses |
| 538system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses | 591system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses |
| 539system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses | 592system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses |
| 540system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 541system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses | 593system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 594system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses |
| 542system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses | 595system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses |
| 543system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses | 596system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses |
| 544system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses 545system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses | 597system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses 598system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses |
| 546system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses | 599system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses |
| 547system.cpu.l2cache.overall_misses::total 483 # number of overall misses 548system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles 549system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # number of ReadReq miss cycles 550system.cpu.l2cache.ReadReq_miss_latency::total 22087500 # number of ReadReq miss cycles 551system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5160500 # number of ReadExReq miss cycles 552system.cpu.l2cache.ReadExReq_miss_latency::total 5160500 # number of ReadExReq miss cycles 553system.cpu.l2cache.demand_miss_latency::cpu.inst 17258000 # number of demand (read+write) miss cycles 554system.cpu.l2cache.demand_miss_latency::cpu.data 9990000 # number of demand (read+write) miss cycles 555system.cpu.l2cache.demand_miss_latency::total 27248000 # number of demand (read+write) miss cycles 556system.cpu.l2cache.overall_miss_latency::cpu.inst 17258000 # number of overall miss cycles 557system.cpu.l2cache.overall_miss_latency::cpu.data 9990000 # number of overall miss cycles 558system.cpu.l2cache.overall_miss_latency::total 27248000 # number of overall miss cycles 559system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) | 600system.cpu.l2cache.overall_misses::total 482 # number of overall misses 601system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21890500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4591500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadReq_miss_latency::total 26482000 # number of ReadReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5706000 # number of ReadExReq miss cycles 605system.cpu.l2cache.ReadExReq_miss_latency::total 5706000 # number of ReadExReq miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.inst 21890500 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::cpu.data 10297500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.demand_miss_latency::total 32188000 # number of demand (read+write) miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.inst 21890500 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::cpu.data 10297500 # number of overall miss cycles 611system.cpu.l2cache.overall_miss_latency::total 32188000 # number of overall miss cycles 612system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) |
| 560system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) | 613system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) |
| 561system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) | 614system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) |
| 562system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 563system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) | 615system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 616system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) |
| 564system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses | 617system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses |
| 565system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses | 618system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses |
| 566system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses 567system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses | 619system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses 620system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses |
| 568system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses | 621system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses |
| 569system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses 570system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses | 622system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses 623system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses |
| 571system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 624system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 572system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses | 625system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses |
| 573system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 574system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 626system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 627system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 575system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses | 628system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses |
| 576system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 629system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 577system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses 578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses | 630system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses 631system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses |
| 579system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 632system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 580system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses 581system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency 582system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency 583system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency 584system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency 585system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency 586system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency 587system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency 588system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency 589system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency 590system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency 591system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency | 633system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65344.776119 # average ReadReq miss latency 635system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71742.187500 # average ReadReq miss latency 636system.cpu.l2cache.ReadReq_avg_miss_latency::total 66370.927318 # average ReadReq miss latency 637system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68746.987952 # average ReadExReq miss latency 638system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68746.987952 # average ReadExReq miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::total 66780.082988 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::total 66780.082988 # average overall miss latency |
| 592system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 598system.cpu.l2cache.fast_writes 0 # number of fast writes performed 599system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 645system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu.l2cache.fast_writes 0 # number of fast writes performed 652system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 600system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses | 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses |
| 601system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses | 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses |
| 602system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses | 655system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses |
| 603system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 604system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses | 656system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses |
| 605system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses | 658system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses |
| 606system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses | 659system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses |
| 607system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses 608system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses | 660system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses |
| 609system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses | 662system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses |
| 610system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses 611system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099263 # number of ReadReq MSHR miss cycles 612system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042283 # number of ReadReq MSHR miss cycles 613system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141546 # number of ReadReq MSHR miss cycles 614system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145788 # number of ReadExReq MSHR miss cycles 615system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145788 # number of ReadExReq MSHR miss cycles 616system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099263 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188071 # number of demand (read+write) MSHR miss cycles 618system.cpu.l2cache.demand_mshr_miss_latency::total 21287334 # number of demand (read+write) MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099263 # number of overall MSHR miss cycles 620system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188071 # number of overall MSHR miss cycles 621system.cpu.l2cache.overall_mshr_miss_latency::total 21287334 # number of overall MSHR miss cycles 622system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses | 663system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses 664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17748750 # number of ReadReq MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3809500 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21558250 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4697250 # number of ReadExReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4697250 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17748750 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8506750 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::total 26255500 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17748750 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8506750 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::total 26255500 # number of overall MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses |
| 623system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 624system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses | 677system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses |
| 625system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 626system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 627system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses | 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses |
| 628system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 629system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses 630system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses | 682system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses |
| 631system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 632system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses 633system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38985.901786 # average ReadReq mshr miss latency 634system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63160.671875 # average ReadReq mshr miss latency 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42853.865000 # average ReadReq mshr miss latency 636system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.253012 # average ReadExReq mshr miss latency 637system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.253012 # average ReadExReq mshr miss latency 638system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency 639system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency 640system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency 641system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency 642system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency 643system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency | 685system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56593.373494 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency |
| 644system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 645system.cpu.dcache.replacements 0 # number of replacements | 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.dcache.replacements 0 # number of replacements |
| 646system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use 647system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. | 699system.cpu.dcache.tagsinuse 98.861742 # Cycle average of tags in use 700system.cpu.dcache.total_refs 4001 # Total number of references to valid blocks. |
| 648system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. | 701system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. |
| 649system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks. | 702system.cpu.dcache.avg_refs 27.217687 # Average number of references to valid blocks. |
| 650system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 703system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 651system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor 652system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy 653system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy 654system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits 655system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits | 704system.cpu.dcache.occ_blocks::cpu.data 98.861742 # Average occupied blocks per requestor 705system.cpu.dcache.occ_percent::cpu.data 0.024136 # Average percentage of cache occupancy 706system.cpu.dcache.occ_percent::total 0.024136 # Average percentage of cache occupancy 707system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits |
| 656system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 657system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 658system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 659system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits | 709system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 711system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 712system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits |
| 660system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits 661system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits 662system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits 663system.cpu.dcache.overall_hits::total 4011 # number of overall hits 664system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses 665system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses | 713system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits 714system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits 715system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits 716system.cpu.dcache.overall_hits::total 3995 # number of overall hits 717system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 718system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses |
| 666system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 667system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses | 719system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 720system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses |
| 668system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses 669system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses 670system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses 671system.cpu.dcache.overall_misses::total 540 # number of overall misses 672system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles 673system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles 674system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles 675system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles 676system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles 677system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles 678system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles 679system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles 680system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses) 681system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses) | 721system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses 722system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses 723system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses 724system.cpu.dcache.overall_misses::total 535 # number of overall misses 725system.cpu.dcache.ReadReq_miss_latency::cpu.data 7949500 # number of ReadReq miss cycles 726system.cpu.dcache.ReadReq_miss_latency::total 7949500 # number of ReadReq miss cycles 727system.cpu.dcache.WriteReq_miss_latency::cpu.data 24575974 # number of WriteReq miss cycles 728system.cpu.dcache.WriteReq_miss_latency::total 24575974 # number of WriteReq miss cycles 729system.cpu.dcache.demand_miss_latency::cpu.data 32525474 # number of demand (read+write) miss cycles 730system.cpu.dcache.demand_miss_latency::total 32525474 # number of demand (read+write) miss cycles 731system.cpu.dcache.overall_miss_latency::cpu.data 32525474 # number of overall miss cycles 732system.cpu.dcache.overall_miss_latency::total 32525474 # number of overall miss cycles 733system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) |
| 682system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 683system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 684system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 685system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) | 735system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 737system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 738system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) |
| 686system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses 687system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses 688system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses 689system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses 690system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses 691system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses | 739system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses 740system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses 741system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses 742system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses 743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses 744system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses |
| 692system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 693system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses | 745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 746system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses |
| 694system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses 695system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses 696system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses 697system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses 698system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency 699system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency 700system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency 701system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency 702system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency 703system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency 704system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency 705system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency 706system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked | 747system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses 748system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses 749system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses 750system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses 751system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency 752system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency 753system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency 754system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency 755system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency 756system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency 757system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency 758system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency 759system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked |
| 707system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 709system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 760system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 762system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 710system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked | 763system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked |
| 711system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.dcache.fast_writes 0 # number of fast writes performed 713system.cpu.dcache.cache_copies 0 # number of cache copies performed | 764system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 765system.cpu.dcache.fast_writes 0 # number of fast writes performed 766system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 714system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 715system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits | 767system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 768system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits |
| 716system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 717system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits | 769system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 770system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits |
| 718system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits 719system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits 720system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits 721system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits | 771system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits 772system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits 773system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits 774system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits |
| 722system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 723system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 724system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 725system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 726system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 727system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 728system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 729system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 775system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 776system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 777system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 778system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 779system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 780system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 781system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 782system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 730system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles 731system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles 732system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles 733system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles 734system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles 735system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles 736system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles 737system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles 738system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses 739system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses | 783system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles 784system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles 785system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles 786system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles 790system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles 791system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses 792system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses |
| 740system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 741system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses | 793system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 794system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses |
| 742system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses 743system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses 744system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses 745system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses 746system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency 747system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency 748system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency 749system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency 751system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency 753system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency | 795system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses 796system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses 797system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses 798system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency 800system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency 802system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency |
| 754system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 755 756---------- End Simulation Statistics ---------- | 807system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 808 809---------- End Simulation Statistics ---------- |