| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 23180500 # Number of ticks simulated 5final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23775500 # Number of ticks simulated 5final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 20805 # Simulator instruction rate (inst/s) 8host_op_rate 20805 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33406458 # Simulator tick rate (ticks/s) 10host_mem_usage 278444 # Number of bytes of host memory used 11host_seconds 0.69 # Real time elapsed on the host | 7host_inst_rate 69212 # Simulator instruction rate (inst/s) 8host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 113962469 # Simulator tick rate (ticks/s) 10host_mem_usage 232268 # Number of bytes of host memory used 11host_seconds 0.21 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 483 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30912 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 30system.physmem.readReqs 483 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30912 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 23120500 # Total gap between requests | 73system.physmem.totGap 23715500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 483 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 11 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 483 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 11 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 101system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 47 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 104system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 47 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 3040483 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests 169system.physmem.totBusLat 1932000 # Total cycles spent in databus access 170system.physmem.totBankLat 8008000 # Total cycles spent in bank access 171system.physmem.avgQLat 6295.00 # Average queueing delay per request 172system.physmem.avgBankLat 16579.71 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26874.71 # Average memory access latency 175system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s | 167system.physmem.totQLat 4632480 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests 169system.physmem.totBusLat 2415000 # Total cycles spent in databus access 170system.physmem.totBankLat 8566250 # Total cycles spent in bank access 171system.physmem.avgQLat 9591.06 # Average queueing delay per request 172system.physmem.avgBankLat 17735.51 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 32326.56 # Average memory access latency 175system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s |
| 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 8.33 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.56 # Average read queue length over time | 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 10.16 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.66 # Average read queue length over time |
| 182system.physmem.avgWrQLen 0.00 # Average write queue length over time | 182system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 183system.physmem.readRowHits 394 # Number of row buffer hits during reads | 183system.physmem.readRowHits 369 # Number of row buffer hits during reads |
| 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 185system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads | 185system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads |
| 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 47868.53 # Average gap between requests 188system.cpu.branchPred.lookups 6759 # Number of BP lookups 189system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted | 187system.physmem.avgGap 49100.41 # Average gap between requests 188system.cpu.branchPred.lookups 6770 # Number of BP lookups 189system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted |
| 190system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect | 190system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect |
| 191system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 2448 # Number of BTB hits | 191system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 2447 # Number of BTB hits |
| 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 194system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage | 194system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage |
| 195system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 197system.cpu.workload.num_syscalls 18 # Number of system calls | 195system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 197system.cpu.workload.num_syscalls 18 # Number of system calls |
| 198system.cpu.numCycles 46362 # number of cpu cycles simulated | 198system.cpu.numCycles 47552 # number of cpu cycles simulated |
| 199system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 200system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 199system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 200system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 201system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss 202system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed 203system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered 204system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken 205system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked 206system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing 207system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked | 201system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss 202system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed 203system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered 204system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken 205system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked 206system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing 207system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked |
| 208system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 208system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 209system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps 210system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched | 209system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps 210system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched |
| 211system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed | 211system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed |
| 212system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total) | 212system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) |
| 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 216system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total) | 216system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) |
| 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 228system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle 230system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 8405 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing 236system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode 237system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 8008 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking 243system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename | 228system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle 230system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 8402 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing 236system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode 237system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 8002 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking 243system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename |
| 244system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full | 244system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full |
| 245system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full 246system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed 247system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made 248system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups | 245system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full 246system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed 247system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made 248system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups |
| 249system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed | 249system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed |
| 250system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing | 250system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing |
| 251system.cpu.rename.serializingInsts 691 # count of serializing insts renamed 252system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed | 251system.cpu.rename.serializingInsts 691 # count of serializing insts renamed 252system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed |
| 253system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer 254system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. 255system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit. | 253system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer 254system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. 255system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. |
| 256system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 257system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 256system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 257system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 258system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec) | 258system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) |
| 259system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ | 259system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ |
| 260system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued 261system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued 262system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling 263system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph | 260system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued 261system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued 262system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling 263system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph |
| 264system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed | 264system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed |
| 265system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle | 265system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle |
| 268system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 268system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 269system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle | 269system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle |
| 277system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 277system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 281system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle | 281system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle |
| 282system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 283system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available 284system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available 285system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 309system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available 312system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available 313system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available 314system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 315system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 316system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 282system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 283system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available 284system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available 285system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 309system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available 312system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available 313system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available 314system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 315system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 316system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 317system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued 318system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued 319system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued 346system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued 347system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued | 317system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued 318system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued 319system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued 346system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued 347system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued |
| 348system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 349system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 348system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 349system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 350system.cpu.iq.FU_type_0::total 21285 # Type of FU issued 351system.cpu.iq.rate 0.459104 # Inst issue rate | 350system.cpu.iq.FU_type_0::total 21278 # Type of FU issued 351system.cpu.iq.rate 0.447468 # Inst issue rate |
| 352system.cpu.iq.fu_busy_cnt 153 # FU busy when requested | 352system.cpu.iq.fu_busy_cnt 153 # FU busy when requested |
| 353system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst) 354system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads 355system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes | 353system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) 354system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads 355system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes |
| 356system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses 357system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 358system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 359system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 356system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses 357system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 358system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 359system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 360system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses | 360system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses |
| 361system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 362system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores 363system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 361system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 362system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores 363system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 364system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed | 364system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed |
| 365system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 366system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations | 365system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 366system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations |
| 367system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed | 367system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed |
| 368system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 369system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 370system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 371system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked 372system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 368system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 369system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 370system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 371system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked 372system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 373system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing 374system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking | 373system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing 374system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking |
| 375system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking | 375system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking |
| 376system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ | 376system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ |
| 377system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch | 377system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch |
| 378system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions 379system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions | 378system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions 379system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions |
| 380system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions 381system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 382system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 383system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations 384system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly 385system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly 386system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute | 380system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions 381system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 382system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 383system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations 384system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly 385system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly 386system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute |
| 387system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions 388system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed 389system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute | 387system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions 388system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed 389system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute |
| 390system.cpu.iew.exec_swp 0 # number of swp insts executed | 390system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 391system.cpu.iew.exec_nop 1139 # number of nop insts executed 392system.cpu.iew.exec_refs 5276 # number of memory reference insts executed 393system.cpu.iew.exec_branches 4247 # Number of branches executed 394system.cpu.iew.exec_stores 2055 # Number of stores executed 395system.cpu.iew.exec_rate 0.435853 # Inst execution rate 396system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit | 391system.cpu.iew.exec_nop 1136 # number of nop insts executed 392system.cpu.iew.exec_refs 5272 # number of memory reference insts executed 393system.cpu.iew.exec_branches 4246 # Number of branches executed 394system.cpu.iew.exec_stores 2053 # Number of stores executed 395system.cpu.iew.exec_rate 0.424882 # Inst execution rate 396system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit |
| 397system.cpu.iew.wb_count 19647 # cumulative count of insts written-back | 397system.cpu.iew.wb_count 19647 # cumulative count of insts written-back |
| 398system.cpu.iew.wb_producers 9210 # num instructions producing a value 399system.cpu.iew.wb_consumers 11373 # num instructions consuming a value | 398system.cpu.iew.wb_producers 9208 # num instructions producing a value 399system.cpu.iew.wb_consumers 11364 # num instructions consuming a value |
| 400system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 400system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 401system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle 402system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back | 401system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle 402system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back |
| 403system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 403system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 404system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit | 404system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit |
| 405system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 406system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted | 405system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 406system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted |
| 407system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle | 407system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle |
| 410system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 410system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 411system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle | 411system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle |
| 419system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 419system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 423system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle | 423system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle |
| 424system.cpu.commit.committedInsts 15162 # Number of instructions committed 425system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 426system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 427system.cpu.commit.refs 3673 # Number of memory references committed 428system.cpu.commit.loads 2225 # Number of loads committed 429system.cpu.commit.membars 0 # Number of memory barriers committed 430system.cpu.commit.branches 3358 # Number of branches committed 431system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 432system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 433system.cpu.commit.function_calls 187 # Number of function calls committed. 434system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached 435system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 424system.cpu.commit.committedInsts 15162 # Number of instructions committed 425system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 426system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 427system.cpu.commit.refs 3673 # Number of memory references committed 428system.cpu.commit.loads 2225 # Number of loads committed 429system.cpu.commit.membars 0 # Number of memory barriers committed 430system.cpu.commit.branches 3358 # Number of branches committed 431system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 432system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 433system.cpu.commit.function_calls 187 # Number of function calls committed. 434system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached 435system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 436system.cpu.rob.rob_reads 54162 # The number of ROB reads 437system.cpu.rob.rob_writes 50836 # The number of ROB writes | 436system.cpu.rob.rob_reads 54359 # The number of ROB reads 437system.cpu.rob.rob_writes 50813 # The number of ROB writes |
| 438system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself | 438system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 439system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling | 439system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 440system.cpu.committedInsts 14436 # Number of Instructions Simulated 441system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 442system.cpu.committedInsts_total 14436 # Number of Instructions Simulated | 440system.cpu.committedInsts 14436 # Number of Instructions Simulated 441system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 442system.cpu.committedInsts_total 14436 # Number of Instructions Simulated |
| 443system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction 444system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads 445system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle 446system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads 447system.cpu.int_regfile_reads 32290 # number of integer regfile reads | 443system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction 444system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads 445system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle 446system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads 447system.cpu.int_regfile_reads 32289 # number of integer regfile reads |
| 448system.cpu.int_regfile_writes 17967 # number of integer regfile writes | 448system.cpu.int_regfile_writes 17967 # number of integer regfile writes |
| 449system.cpu.misc_regfile_reads 6967 # number of misc regfile reads | 449system.cpu.misc_regfile_reads 6962 # number of misc regfile reads |
| 450system.cpu.misc_regfile_writes 569 # number of misc regfile writes 451system.cpu.icache.replacements 0 # number of replacements | 450system.cpu.misc_regfile_writes 569 # number of misc regfile writes 451system.cpu.icache.replacements 0 # number of replacements |
| 452system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use 453system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. | 452system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use 453system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. |
| 454system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. | 454system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. |
| 455system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. | 455system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. |
| 456system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 456system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 457system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor 458system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy 459system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy 460system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits 461system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits 462system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits 463system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits 464system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits 465system.cpu.icache.overall_hits::total 4845 # number of overall hits 466system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses 467system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses 468system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses 469system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses 470system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses 471system.cpu.icache.overall_misses::total 493 # number of overall misses 472system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles 473system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles 474system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles 475system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles 476system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles 477system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles 478system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses) 479system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses) 480system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses 481system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses 482system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses 483system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses 484system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses 485system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses 486system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses 487system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses 488system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses 489system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses 490system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency 491system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency 492system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency 493system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency 494system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency 495system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency | 457system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor 458system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy 459system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy 460system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits 461system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits 462system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits 463system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits 464system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits 465system.cpu.icache.overall_hits::total 4850 # number of overall hits 466system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses 467system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses 468system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses 469system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses 470system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses 471system.cpu.icache.overall_misses::total 491 # number of overall misses 472system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles 473system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles 474system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles 475system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles 476system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles 477system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles 478system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) 479system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) 480system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses 481system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses 482system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses 483system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses 484system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses 485system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses 486system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses 487system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses 488system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses 489system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses 490system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency 491system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency 492system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency 493system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency 494system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency 495system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency |
| 496system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 497system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 498system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 499system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 500system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 501system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 502system.cpu.icache.fast_writes 0 # number of fast writes performed 503system.cpu.icache.cache_copies 0 # number of cache copies performed | 496system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 497system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 498system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 499system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 500system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 501system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 502system.cpu.icache.fast_writes 0 # number of fast writes performed 503system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 504system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits 505system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits 506system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits 507system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits 508system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits 509system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits | 504system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits 505system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits 506system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits 507system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits 508system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits 509system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits |
| 510system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 511system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 512system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 513system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 514system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 515system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses | 510system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 511system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 512system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 513system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 514system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 515system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses |
| 516system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles 517system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles 518system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles 519system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles 520system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles 521system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses 523system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses 524system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses 525system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses 526system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses 527system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses 528system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency 529system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency 530system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency 531system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency 532system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency 533system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency | 516system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles 517system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles 518system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles 519system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles 520system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles 521system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses 523system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses 524system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses 525system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses 526system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses 527system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses 528system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency 529system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency 530system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency 531system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency 532system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency 533system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency |
| 534system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 535system.cpu.l2cache.replacements 0 # number of replacements | 534system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 535system.cpu.l2cache.replacements 0 # number of replacements |
| 536system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use | 536system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use |
| 537system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 538system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. 539system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. 540system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 537system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 538system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. 539system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. 540system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 541system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor 542system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor 543system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy 545system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy | 541system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor 542system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor 543system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy 545system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy |
| 546system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 548system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 549system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 550system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 551system.cpu.l2cache.overall_hits::total 2 # number of overall hits 552system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses 553system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses 554system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses 555system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 556system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 557system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses 558system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses 559system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses 560system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses 561system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses 562system.cpu.l2cache.overall_misses::total 483 # number of overall misses | 546system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 548system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 549system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 550system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 551system.cpu.l2cache.overall_hits::total 2 # number of overall hits 552system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses 553system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses 554system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses 555system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 556system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 557system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses 558system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses 559system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses 560system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses 561system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses 562system.cpu.l2cache.overall_misses::total 483 # number of overall misses |
| 563system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles 564system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles 565system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles 566system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles 567system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles 568system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles 569system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles 570system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles 571system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles 572system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles 573system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles | 563system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles 564system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # number of ReadReq miss cycles 565system.cpu.l2cache.ReadReq_miss_latency::total 22087500 # number of ReadReq miss cycles 566system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5160500 # number of ReadExReq miss cycles 567system.cpu.l2cache.ReadExReq_miss_latency::total 5160500 # number of ReadExReq miss cycles 568system.cpu.l2cache.demand_miss_latency::cpu.inst 17258000 # number of demand (read+write) miss cycles 569system.cpu.l2cache.demand_miss_latency::cpu.data 9990000 # number of demand (read+write) miss cycles 570system.cpu.l2cache.demand_miss_latency::total 27248000 # number of demand (read+write) miss cycles 571system.cpu.l2cache.overall_miss_latency::cpu.inst 17258000 # number of overall miss cycles 572system.cpu.l2cache.overall_miss_latency::cpu.data 9990000 # number of overall miss cycles 573system.cpu.l2cache.overall_miss_latency::total 27248000 # number of overall miss cycles |
| 574system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 575system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 576system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) 577system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 578system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 579system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 580system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 581system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 588system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 590system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses 591system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 592system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses 593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses 594system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 595system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses | 574system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 575system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 576system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) 577system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 578system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 579system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 580system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 581system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 588system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 589system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 590system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses 591system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 592system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses 593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses 594system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 595system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses |
| 596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency 597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency 598system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency 599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency 600system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency 601system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency 602system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency 603system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency 604system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency 605system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency 606system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency | 596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency 597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency 598system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency 599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency 600system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency 601system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency 602system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency 603system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency 604system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency 605system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency 606system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency |
| 607system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 608system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 609system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 610system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 611system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 612system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 613system.cpu.l2cache.fast_writes 0 # number of fast writes performed 614system.cpu.l2cache.cache_copies 0 # number of cache copies performed 615system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 616system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 617system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses 618system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 619system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 620system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 621system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 622system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses 623system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 624system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 625system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses | 607system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 608system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 609system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 610system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 611system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 612system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 613system.cpu.l2cache.fast_writes 0 # number of fast writes performed 614system.cpu.l2cache.cache_copies 0 # number of cache copies performed 615system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 616system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 617system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses 618system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 619system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 620system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 621system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 622system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses 623system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 624system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 625system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses |
| 626system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12529012 # number of ReadReq MSHR miss cycles 627system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2980062 # number of ReadReq MSHR miss cycles 628system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15509074 # number of ReadReq MSHR miss cycles 629system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3397062 # number of ReadExReq MSHR miss cycles 630system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3397062 # number of ReadExReq MSHR miss cycles 631system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12529012 # number of demand (read+write) MSHR miss cycles 632system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6377124 # number of demand (read+write) MSHR miss cycles 633system.cpu.l2cache.demand_mshr_miss_latency::total 18906136 # number of demand (read+write) MSHR miss cycles 634system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12529012 # number of overall MSHR miss cycles 635system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6377124 # number of overall MSHR miss cycles 636system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles | 626system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles 627system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles 628system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles 629system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles 630system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles 631system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles 632system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles 633system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles 634system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles 635system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles 636system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles |
| 637system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses 638system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 639system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses 640system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 641system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 642system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses 643system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 644system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses 645system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses 646system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 647system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses | 637system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses 638system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 639system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses 640system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 641system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 642system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses 643system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 644system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses 645system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses 646system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 647system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses |
| 648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency 649system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency 650system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency 651system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency 652system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency 653system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency 654system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency 655system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency 656system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency 657system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency 658system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency | 648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency 649system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency 650system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency 651system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency 652system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency 653system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency 654system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency 655system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency 656system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency 657system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency 658system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency |
| 659system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cpu.dcache.replacements 0 # number of replacements | 659system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cpu.dcache.replacements 0 # number of replacements |
| 661system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use 662system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks. | 661system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use 662system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. |
| 663system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. | 663system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. |
| 664system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks. | 664system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks. |
| 665system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 665system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 666system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor 667system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy 668system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy 669system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits 670system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits | 666system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor 667system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy 668system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy 669system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits 670system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits |
| 671system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 672system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 673system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 674system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits | 671system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 672system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 673system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 674system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits |
| 675system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits 676system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits 677system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits 678system.cpu.dcache.overall_hits::total 4013 # number of overall hits 679system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses 680system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses | 675system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits 676system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits 677system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits 678system.cpu.dcache.overall_hits::total 4011 # number of overall hits 679system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses 680system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses |
| 681system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 682system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses | 681system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 682system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses |
| 683system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses 684system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses 685system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses 686system.cpu.dcache.overall_misses::total 539 # number of overall misses 687system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles 688system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles 689system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles 690system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles 691system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles 692system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles 693system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles 694system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles 695system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses) 696system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses) | 683system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses 684system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses 685system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses 686system.cpu.dcache.overall_misses::total 540 # number of overall misses 687system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles 688system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles 689system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles 690system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles 691system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles 692system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles 693system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles 694system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles 695system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses) 696system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses) |
| 697system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 698system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 699system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 700system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) | 697system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 698system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 699system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 700system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) |
| 701system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses 702system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses 703system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses 704system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses 705system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses 706system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses | 701system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses 702system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses 703system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses 704system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses 705system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses 706system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses |
| 707system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 708system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses | 707system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 708system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses |
| 709system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses 710system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses 711system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses 712system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses 713system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency 714system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency 715system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency 717system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency 718system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency 719system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency 720system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency 721system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked | 709system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses 710system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses 711system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses 712system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses 713system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency 714system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency 715system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency 717system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency 718system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency 719system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency 720system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency 721system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked |
| 722system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 724system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 722system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked 724system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 725system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked | 725system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked |
| 726system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu.dcache.fast_writes 0 # number of fast writes performed 728system.cpu.dcache.cache_copies 0 # number of cache copies performed | 726system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu.dcache.fast_writes 0 # number of fast writes performed 728system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 729system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits 730system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits | 729system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 730system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits |
| 731system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 732system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits | 731system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 732system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits |
| 733system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits 734system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits 735system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits 736system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits | 733system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits 734system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits 735system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits 736system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits |
| 737system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 738system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 739system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 740system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 741system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 742system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 743system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 744system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 737system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 738system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 739system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 740system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 741system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 742system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 743system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 744system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 745system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles 746system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles 747system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles 748system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles 752system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles 753system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses | 745system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles 746system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles 747system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles 748system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles 752system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles 753system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses |
| 755system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses | 755system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses |
| 757system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses 758system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses 759system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses 760system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses 761system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency 762system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency 763system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency 764system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency 765system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency 766system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency 767system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency 768system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency | 757system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses 758system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses 759system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses 760system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses 761system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency 762system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency 763system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency 764system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency 765system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency 766system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency 767system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency 768system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency |
| 769system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 770 771---------- End Simulation Statistics ---------- | 769system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 770 771---------- End Simulation Statistics ---------- |